diff options
| author | Kevin Chiu <Kevin.Chiu@quantatw.com> | 2020-08-26 18:10:33 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-08-30 17:03:35 +0000 |
| commit | 144c5aeca2955e694de600b862d0133606900643 (patch) | |
| tree | b9d1b224573ea51a2cd92fd73ce39bab9ddc4d8f /src/mainboard/google/kukui/sdram_params | |
| parent | 9256e51f48550c83f5425550b8feee9fc2b7366c (diff) | |
mb/google/kukui: Add LPDDR4X Samsung K4UBE3D4AA-MGCR 4GB support for burnet/esche
Add LPDDR4x DRAM index#0 Samsung K4UBE3D4AA-MGCR 4GB
BUG=b:165956924
BRANCH=kukui
TEST=emerge-jacuzzi coreboot
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I644b65d77b79891ed65215d810b970fe43b29e3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44821
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/kukui/sdram_params')
| -rw-r--r-- | src/mainboard/google/kukui/sdram_params/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB.c | 27 |
2 files changed, 28 insertions, 0 deletions
diff --git a/src/mainboard/google/kukui/sdram_params/Makefile.inc b/src/mainboard/google/kukui/sdram_params/Makefile.inc index 12019a2d8e..719b3c29e9 100644 --- a/src/mainboard/google/kukui/sdram_params/Makefile.inc +++ b/src/mainboard/google/kukui/sdram_params/Makefile.inc @@ -1,4 +1,5 @@ sdram-params := +sdram-params += sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB sdram-params += sdram-lpddr4x-H9HCNNNCPMALHR-4GB sdram-params += sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB sdram-params += sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB.c new file mode 100644 index 0000000000..1734797042 --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCR-4GB.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_param.h> + +struct sdram_params params = { + .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .frequency = 1600, + .ddr_geometry = DDR_TYPE_2CH_2RK_4GB_2_2, + .wr_level = { + [CHANNEL_A] = { {0x22, 0x1C}, {0x23, 0x1D} }, + [CHANNEL_B] = { {0x26, 0x23}, {0x26, 0x23} } + }, + .cbt_cs_dly = { + [CHANNEL_A] = {0x6, 0x5}, + [CHANNEL_B] = {0x6, 0x6} + }, + .cbt_final_vref = { + [CHANNEL_A] = {0x56, 0x58}, + [CHANNEL_B] = {0x58, 0x56} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_NORMAL_MODE, + .delay_cell_unit = 868, +}; |