diff options
author | Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> | 2021-01-05 10:47:27 +0800 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-15 11:29:34 +0000 |
commit | 769320d1c492b60119f7e7e779971836ed98a63d (patch) | |
tree | 6e46910b477c3fae23136fa19f10ef0f652f7761 /src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB.c | |
parent | 5ff588dbc10bbf69f140cebf3a584f1ed563b1c5 (diff) |
mb/google/kukui: Add new ddr architecture support for kukui
Two configuration files are added:
1. H9HCNNNFAMMLXR-NEE-8GB: new byte mode
2. MT53E1G32D2NP-046-4GB: new single rank mode
Also initialize the rank number field 'rank_num' for all configs.
BUG=b:165768895
BRANCH=kukui
TEST=DDR boot up correctly on Kukui
Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com>
Change-Id: I1786c1e251e8d6e110cbdce79feeb386db220404
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49108
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB.c')
-rw-r--r-- | src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB.c new file mode 100644 index 0000000000..b440c7f65c --- /dev/null +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_param.h> + +struct sdram_params params = { + .source = DRAMC_PARAM_SOURCE_SDRAM_CONFIG, + .ddr_geometry = DDR_TYPE_2CH_RK0_RK1_BYTE_8GB_4_4, + .frequency = 1600, + .rank_num = 2, + .wr_level = { + [CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} }, + [CHANNEL_B] = { {0x22, 0x1E}, {0x22, 0x1E} } + }, + .cbt_cs_dly = { + [CHANNEL_A] = {0x5, 0x4}, + [CHANNEL_B] = {0x8, 0x8} + }, + .cbt_final_vref = { + [CHANNEL_A] = {0x56, 0x56}, + [CHANNEL_B] = {0x56, 0x56} + }, + .emi_cona_val = 0xF053F154, + .emi_conh_val = 0x44440003, + .emi_conf_val = 0x00421000, + .chn_emi_cona_val = {0x0444F051, 0x0444F051}, + .cbt_mode_extern = CBT_BYTE_MODE1, + .delay_cell_unit = 868, +}; |