diff options
| author | Weiyi Lu <weiyi.lu@mediatek.com> | 2020-06-19 15:28:55 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-10-08 11:58:42 +0000 |
| commit | 86b3bf10e60c137b01b81a37ce9827757f6af42d (patch) | |
| tree | ea5e759fc4615a2629fac4c85503510c77b63cd0 /src/mainboard/google/kukui/romstage.c | |
| parent | 83b33f62cf7b125b524b2fbdea5bd8317be0c154 (diff) | |
soc/mediatek: Add function to raise the CPU frequency of MT8192
Rename all mt_pll_raise_ca53_freq() into mt_pll_raise_little_cpu_freq().
Implement mt_pll_raise_little_cpu_freq() in MT8192.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: I97d9a61f39f2eb27f0c6f911a9199bf0eaae4fbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/mainboard/google/kukui/romstage.c')
| -rw-r--r-- | src/mainboard/google/kukui/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 1a2127d735..b9c0d2c834 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -57,7 +57,7 @@ void platform_romstage_main(void) mt6358_init(); /* Adjust VSIM2 down to 2.7V because it is shared with IT6505. */ pmic_set_vsim2_cali(2700); - mt_pll_raise_ca53_freq(1989 * MHz); + mt_pll_raise_little_cpu_freq(1989 * MHz); pmic_init_scp_voltage(); rtc_boot(); mt_mem_init(&dparam_ops); |