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authorTristan Shieh <tristan.shieh@mediatek.com>2018-10-19 17:29:23 +0800
committerPatrick Georgi <pgeorgi@google.com>2018-12-05 13:35:59 +0000
commit0688ab8d95f18f718510cc17aeb01a47519a9a5a (patch)
tree05fcd7af442ef1f32e85b34d1cdf5ac25371d434 /src/mainboard/google/kukui/gpio.h
parent3a065f1a76feb4f23af6708caef5f912292610fd (diff)
google/kukui: Support TPM
Init SPI bus 0 to connect TPM, configure interrupt type of GPIO CR50_IRQ, implement tis_plat_irq_status(), and set up chromeos GPIO table for TPM interrupt. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui. Change-Id: Ieaa6ae65fbfb5ab6323e226e8171dd7a992c3a39 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/29192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/google/kukui/gpio.h')
-rw-r--r--src/mainboard/google/kukui/gpio.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/kukui/gpio.h b/src/mainboard/google/kukui/gpio.h
index a2f77606ac..20a50a6923 100644
--- a/src/mainboard/google/kukui/gpio.h
+++ b/src/mainboard/google/kukui/gpio.h
@@ -20,6 +20,7 @@
#define EC_IRQ GPIO(PERIPHERAL_EN1)
#define EC_IN_RW GPIO(PERIPHERAL_EN14)
+#define CR50_IRQ GPIO(PERIPHERAL_EN3)
void setup_chromeos_gpios(void);