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authorSaurabh Mishra <mishra.saurabh@intel.corp-partner.google.com>2024-07-24 20:26:27 +0530
committerSubrata Banik <subratabanik@google.com>2024-08-16 06:21:08 +0000
commitde1a74454ffaaca11c6735814ad1b97cc6e522cd (patch)
treebc8a064a8d5d4412722f595570bb34ffca12f3b6 /src/mainboard/google/kukui/chromeos.c
parent4c749d765da3be894b5ae22d08f5d286881a6e19 (diff)
soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
List of changes: 1. Add required SoC programming till romstage 2. Include only required headers into include/soc 3. Fill required FSP-M UPD to call FSP-M API 4. Ref: Processor EDS documents Panther Lake U/H 12Xe/H 4Xe External Design Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and Volume 2 of 2 #813030 BUG=b:348678529 TEST=Verified on IntelĀ® SimicsĀ® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
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