diff options
| author | Simon Glass <sjg@chromium.org> | 2018-05-01 11:54:29 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-05-02 20:48:41 +0000 |
| commit | fe588985f2e9a9ba4c2839f5e65c3f69d96751b3 (patch) | |
| tree | 6561354ac3378f4286c39c32268b043ef322ddb0 /src/mainboard/google/kahlee | |
| parent | 38d875f38789892d2e25b3bbba330733965025ac (diff) | |
mb/google/kahlee/variants/grunt: Enable BayHub720 driver
Enable this driver along with power saving.
BUG=b:73726008
BRANCH=none
TEST=boot and see this message:
BayHub BH720: Power-saving enabled 110103
From linux:
$ iotools pci_read32 2 0 0 0x90
0x00110103
Change-Id: I850e923f73e01fe629d66ad61b65afa58035845c
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/25967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/kahlee')
| -rw-r--r-- | src/mainboard/google/kahlee/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/google/kahlee/variants/grunt/devicetree.cb | 7 |
2 files changed, 7 insertions, 1 deletions
diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 22925f4eb9..24881b57d0 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -36,6 +36,7 @@ config BOARD_GOOGLE_BASEBOARD_KAHLEE select SOC_AMD_PSP_SELECTABLE_SMU_FW select SOC_AMD_SMU_FANLESS select HAVE_ACPI_RESUME + select DRIVERS_GENERIC_BH720 if BOARD_GOOGLE_GRUNT if BOARD_GOOGLE_BASEBOARD_KAHLEE diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb index cfc3198b25..151d902e0c 100644 --- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb @@ -62,7 +62,12 @@ chip soc/amd/stoneyridge device pci 2.1 on end # device pci 2.2 on end # device pci 2.3 on end # - device pci 2.4 on end # + device pci 2.4 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end + end # device pci 2.5 on end # device pci 8.0 on end # PSP device pci 9.0 on end # PCIe Host Bridge |