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authorAngel Pons <th3fanbus@gmail.com>2021-01-22 15:24:48 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-01-28 09:18:18 +0000
commit73c967665b6347490a22371c558f34c022836181 (patch)
treef53f66951fcdd8235f77e0a16fb1340e434a54b0 /src/mainboard/google/kahlee
parenta4ecf9654e5ee84958dc8dfea3c1391da61bd263 (diff)
bayhub bh720: Factor out common HS200 init code
Except for one debug print in sarien, both functions are identical. Move them to driver code to avoid unnecessary redundancy. Change-Id: I82635a289e3c05119eab4ee1f7a6bf3a8a1725c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/kahlee')
-rw-r--r--src/mainboard/google/kahlee/variants/baseboard/mainboard.c49
1 files changed, 0 insertions, 49 deletions
diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c
index 860190a2b6..7893449f7d 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c
@@ -7,9 +7,6 @@
#include <gpio.h>
#include <smbios.h>
#include <variant/gpio.h>
-#include <device/mmio.h>
-#include <device/pci_ops.h>
-#include <drivers/generic/bayhub/bh720.h>
uint32_t sku_id(void)
{
@@ -32,52 +29,6 @@ void variant_mainboard_suspend_resume(void)
gpio_set(GPIO_133, 0);
}
-void board_bh720(struct device *dev)
-{
- u32 sdbar;
- u32 bh720_pcr_data;
-
- sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
-
- /* Enable Memory Access Function */
- write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000);
- write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000);
- write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0);
-
- /* Set EMMC VCCQ 1.8V PCR 0x308[4] */
- write32((void *)(sdbar + BH720_MEM_RW_ADR),
- BH720_MEM_RW_READ | BH720_PCR_EMMC_SETTING);
- bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA));
- write32((void *)(sdbar + BH720_MEM_RW_DATA),
- bh720_pcr_data | BH720_PCR_EMMC_SETTING_1_8V);
- write32((void *)(sdbar + BH720_MEM_RW_ADR),
- BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING);
-
- /* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */
- write32((void *)(sdbar + BH720_MEM_RW_ADR),
- BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL);
- bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA));
- bh720_pcr_data &= 0x0000FFFF;
- bh720_pcr_data |= 0x2510 << 16;
- write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data);
- write32((void *)(sdbar + BH720_MEM_RW_ADR),
- BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL);
-
- /* Use PLL Base clock PCR 0x3E4[22] = 1 */
- write32((void *)(sdbar + BH720_MEM_RW_ADR),
- BH720_MEM_RW_READ | BH720_PCR_CSR);
- bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA));
- write32((void *)(sdbar + BH720_MEM_RW_DATA),
- bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL);
- write32((void *)(sdbar + BH720_MEM_RW_ADR),
- BH720_MEM_RW_WRITE | BH720_PCR_CSR);
-
- /* Disable Memory Access */
- write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001);
- write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0);
- write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000);
-}
-
const char *smbios_mainboard_manufacturer(void)
{
static char oem_bin_data[11];