diff options
author | Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> | 2018-04-03 08:51:48 -0700 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2018-04-13 16:44:42 +0000 |
commit | 48e074975d518239b69a4a303cce5ace6b500f13 (patch) | |
tree | 4e8fc4c33cd801a1ee08dc56276ffa791cbfa7c1 /src/mainboard/google/kahlee | |
parent | 0beb62760d97833303650f67ceda938cf83a1659 (diff) |
mb/google/kahlee: Fix IRQ routing
ACPI interrupt routing file routing.asl is not reflecting AGESA settings to
the NB Interrupt Routing Registers. The AGESA settings are:
Device self INTA INTB INTC INTD
GPP 0 23 0 1 2 3
GPP 1 24 8 9 10 11
GPP 2 25 16 17 18 19
GPP 3 26 24 25 26 27
GPP 4 23 3 0 1 2
HDA none 22 23 20 21
GBIF none 6 7 4 5
Fix the routing table, considering that NB IOAPIC starts at interrupt 24.
BUG=b:74104946
TEST=Build and boot to a modified grunt board to enable the emmc. Then used
"cat /proc/interrupts" to get active interrupts. Also checked IOAPIC
redirection registers, which are now being programmed.
Change-Id: I60847c46f3f938f9e97d7b323b27d20e36aa2d02
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/kahlee')
-rw-r--r-- | src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl | 100 |
1 files changed, 51 insertions, 49 deletions
diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl index c61bc4bb6c..433e2333f9 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl @@ -29,15 +29,17 @@ Name (PR0, Package() /* Bus 0, Dev 1, Func 0 - PCI Bridge for Internal Graphics(IGP) */ /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ - Package() { 0x0001FFFF, 0, INTB, 0 }, - Package() { 0x0001FFFF, 1, INTC, 0 }, + Package() { 0x0001FFFF, 0, INTG, 0 }, + Package() { 0x0001FFFF, 1, INTH, 0 }, + Package() { 0x0001FFFF, 2, INTE, 0 }, + Package() { 0x0001FFFF, 3, INTF, 0 }, /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ - Package() { 0x0002FFFF, 0, INTC, 0 }, - Package() { 0x0002FFFF, 1, INTD, 0 }, - Package() { 0x0002FFFF, 2, INTA, 0 }, - Package() { 0x0002FFFF, 3, INTB, 0 }, + Package() { 0x0002FFFF, 0, INTH, 0 }, + Package() { 0x0002FFFF, 1, INTA, 0 }, + Package() { 0x0002FFFF, 2, INTB, 0 }, + Package() { 0x0002FFFF, 3, INTC, 0 }, /* FCH devices */ /* Bus 0, Dev 20 - F0:SMBus/ACPI;F3:LPC;F7:SD */ @@ -48,11 +50,9 @@ Name (PR0, Package() /* Bus 0, Dev 18 Func 0 - USB: EHCI */ Package() { 0x0012FFFF, 0, INTC, 0 }, - Package() { 0x0012FFFF, 1, INTB, 0 }, /* Bus 0, Dev 10 Func 0 - USB: xHCI */ Package() { 0x0010FFFF, 0, INTC, 0 }, - Package() { 0x0010FFFF, 1, INTB, 0 }, /* Bus 0, Dev 17 - SATA controller */ Package() { 0x0011FFFF, 0, INTD, 0 }, @@ -65,14 +65,18 @@ Name (APR0, Package() /* Bus 0, Dev 0 - F15 Host Controller */ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ - Package() { 0x0001FFFF, 0, 0, 43 }, - Package() { 0x0001FFFF, 1, 0, 40 }, + /* IOAPIC2BASE + (group * 4) == 24 + (1 * 4), CDAB swizzle */ + Package() { 0x0001FFFF, 0, 0, 30 }, + Package() { 0x0001FFFF, 1, 0, 31 }, + Package() { 0x0001FFFF, 1, 0, 28 }, + Package() { 0x0001FFFF, 1, 0, 29 }, /* Bus 0, Dev 2 - PCIe Bridges */ - Package() { 0x0002FFFF, 0, 0, 44 }, - Package() { 0x0002FFFF, 1, 0, 45 }, - Package() { 0x0002FFFF, 2, 0, 46 }, - Package() { 0x0002FFFF, 3, 0, 47 }, + /* IOAPIC2BASE + 23 */ + Package() { 0x0002FFFF, 0, 0, 47 }, + Package() { 0x0002FFFF, 1, 0, 48 }, + Package() { 0x0002FFFF, 2, 0, 49 }, + Package() { 0x0002FFFF, 3, 0, 50 }, /* SB devices in APIC mode */ /* Bus 0, Dev 20 - F0:SMBus/ACPI;F3:LPC;F7:SD */ @@ -83,11 +87,9 @@ Name (APR0, Package() /* Bus 0, Dev 18 Func 0 - USB: EHCI */ Package() { 0x0012FFFF, 0, 0, 18 }, - Package() { 0x0012FFFF, 1, 0, 17 }, /* Bus 0, Dev 10 Func 0 - USB: xHCI */ Package() { 0x0010FFFF, 0, 0, 18}, - Package() { 0x0010FFFF, 1, 0, 17}, /* Bus 0, Dev 17 - SATA controller */ Package() { 0x0011FFFF, 0, 0, 19 }, @@ -103,7 +105,7 @@ Name (PS4, Package() Package() { 0x0000FFFF, 3, INTD, 0 }, }) Name (APS4, Package() -{ +{ /* IOAPIC2BASE + (group * 4) == 24 + (0 * 4), no swizzle */ /* PCIe slot - Hooked to PCIe slot 4 */ Package() { 0x0000FFFF, 0, 0, 24 }, Package() { 0x0000FFFF, 1, 0, 25 }, @@ -114,49 +116,49 @@ Name (APS4, Package() /* GPP 1 */ Name (PS5, Package() { - Package() { 0x0000FFFF, 0, INTB, 0 }, - Package() { 0x0000FFFF, 1, INTC, 0 }, - Package() { 0x0000FFFF, 2, INTD, 0 }, - Package() { 0x0000FFFF, 3, INTA, 0 }, + Package() { 0x0000FFFF, 0, INTA, 0 }, + Package() { 0x0000FFFF, 1, INTB, 0 }, + Package() { 0x0000FFFF, 2, INTC, 0 }, + Package() { 0x0000FFFF, 3, INTD, 0 }, }) Name (APS5, Package() -{ - Package() { 0x0000FFFF, 0, 0, 28 }, - Package() { 0x0000FFFF, 1, 0, 29 }, - Package() { 0x0000FFFF, 2, 0, 30 }, - Package() { 0x0000FFFF, 3, 0, 31 }, +{ /* IOAPIC2BASE + (group * 4) == 24 + (2 * 4), no swizzle */ + Package() { 0x0000FFFF, 0, 0, 32 }, + Package() { 0x0000FFFF, 1, 0, 33 }, + Package() { 0x0000FFFF, 2, 0, 34 }, + Package() { 0x0000FFFF, 3, 0, 35 }, }) /* GPP 2 */ Name (PS6, Package() { - Package() { 0x0000FFFF, 0, INTC, 0 }, - Package() { 0x0000FFFF, 1, INTD, 0 }, - Package() { 0x0000FFFF, 2, INTA, 0 }, - Package() { 0x0000FFFF, 3, INTB, 0 }, + Package() { 0x0000FFFF, 0, INTA, 0 }, + Package() { 0x0000FFFF, 1, INTB, 0 }, + Package() { 0x0000FFFF, 2, INTC, 0 }, + Package() { 0x0000FFFF, 3, INTD, 0 }, }) Name (APS6, Package() -{ - Package() { 0x0000FFFF, 0, 0, 32 }, - Package() { 0x0000FFFF, 1, 0, 33 }, - Package() { 0x0000FFFF, 2, 0, 34 }, - Package() { 0x0000FFFF, 3, 0, 35 }, +{ /* IOAPIC2BASE + (group * 4) == 24 + (4 * 4), no swizzle */ + Package() { 0x0000FFFF, 0, 0, 40 }, + Package() { 0x0000FFFF, 1, 0, 41 }, + Package() { 0x0000FFFF, 2, 0, 42 }, + Package() { 0x0000FFFF, 3, 0, 43 }, }) /* GPP 3 */ Name (PS7, Package() { - Package() { 0x0000FFFF, 0, INTD, 0 }, - Package() { 0x0000FFFF, 1, INTA, 0 }, - Package() { 0x0000FFFF, 2, INTB, 0 }, - Package() { 0x0000FFFF, 3, INTC, 0 }, + Package() { 0x0000FFFF, 0, INTA, 0 }, + Package() { 0x0000FFFF, 1, INTB, 0 }, + Package() { 0x0000FFFF, 2, INTC, 0 }, + Package() { 0x0000FFFF, 3, INTD, 0 }, }) Name (APS7, Package() -{ - Package() { 0x0000FFFF, 0, 0, 36 }, - Package() { 0x0000FFFF, 1, 0, 37 }, - Package() { 0x0000FFFF, 2, 0, 38 }, - Package() { 0x0000FFFF, 3, 0, 39 }, +{ /* IOAPIC2BASE + (group * 4) == 24 + (6 * 4), no swizzle */ + Package() { 0x0000FFFF, 0, 0, 48 }, + Package() { 0x0000FFFF, 1, 0, 49 }, + Package() { 0x0000FFFF, 2, 0, 50 }, + Package() { 0x0000FFFF, 3, 0, 51 }, }) /* GPP 4 */ @@ -167,9 +169,9 @@ Name(PS8, Package(){ Package(){0x0000FFFF, 3, INTD, 0 }, }) Name (APS8, Package() -{ - Package() { 0x0000FFFF, 0, 0, 40 }, - Package() { 0x0000FFFF, 1, 0, 41 }, - Package() { 0x0000FFFF, 2, 0, 42 }, - Package() { 0x0000FFFF, 3, 0, 43 }, +{ /* IOAPIC2BASE + (group * 4) == 24 + (0 * 4), DABC swizzle */ + Package() { 0x0000FFFF, 0, 0, 27 }, + Package() { 0x0000FFFF, 1, 0, 24 }, + Package() { 0x0000FFFF, 2, 0, 25 }, + Package() { 0x0000FFFF, 3, 0, 26 }, }) |