mainboard/google/kahlee: Prepare for variants

Move files that are particularly specific to the mainboard into the
variant directory.  Files that only have small areas of mainboard
specific pieces use #if to separate between the boards.

Add memory.c to split out the variant board id into a weak function.
Add baseboard/gpio.h to satisfy the build - this will be updated in the
next commit.

BUG=b:68293392

Change-Id: I7c1beb45f571f2547f3b5b0d7ec78923d0cec761
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

8 files changed, 398 insertions, 0 deletions

diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h
new file mode 100644
index 0000000000..5aca3e88b5
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#ifndef __ACPI__
+#include <soc/gpio.h>
+
+# define MEM_CONFIG0		GPIO_0
+# define MEM_CONFIG1		GPIO_0
+# define MEM_CONFIG2		GPIO_0
+# define MEM_CONFIG3		GPIO_0
+
+/* SPI Write protect */
+#define CROS_WP_GPIO		GPIO_0
+#define GPIO_EC_IN_RW		GPIO_0
+
+#endif /* _ACPI__ */
+
+#define EC_SCI_GPI		0
+
+#define EC_SMI_GPI		0
+
+#endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h
new file mode 100644
index 0000000000..3b4da2636b
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+
+#ifndef __BASEBOARD_VARIANTS_H__
+#define __BASEBOARD_VARIANTS_H__
+
+#include <stddef.h>
+
+size_t variant_board_id(void);
+
+#endif /* __BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc b/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc
new file mode 100644
index 0000000000..94f388912c
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/kahlee/Makefile.inc
@@ -0,0 +1,22 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2017 Google, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+romstage-y += memory.c
+
+ramstage-y += gpio.c
+ramstage-y += memory.c
diff --git a/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb b/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb
new file mode 100644
index 0000000000..4376011797
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/kahlee/devicetree.cb
@@ -0,0 +1,64 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+chip soc/amd/stoneyridge
+
+	register "spdAddrLookup" = "
+	{
+		{ {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0
+	}"
+
+	device cpu_cluster 0 on
+		device lapic 10 on end
+	end
+	device domain 0 on
+		subsystemid 0x1022 0x1410 inherit
+		device pci 0.0 on  end # Root Complex
+		device pci 1.0 on  end # Internal Graphics P2P bridge 0x98e4
+		device pci 1.1 on  end # Internal Multimedia
+		device pci 2.0 on  end # PCIe Host Bridge
+		device pci 2.1 on  end # x4 PCIe slot
+		device pci 2.2 on  end # M.2 slot
+		device pci 2.3 on  end # M.2 slot
+		device pci 2.4 on  end # x1 PCIe slot
+		device pci 2.5 on  end # Cardreader
+		# devices on the NB/SB Link, but on the same pci bus
+		device pci 8.0 on  end # PSP
+		device pci 9.0 on  end # PCIe Host Bridge
+		device pci 9.2 on  end # HDA
+		device pci 10.0 on  end # xHCI
+		device pci 11.0 on  end # SATA
+		device pci 12.0 on  end # EHCI
+		device pci 14.0 on      # SM
+			chip drivers/generic/generic # dimm 0-0-0
+				device i2c 50 on end
+			end
+		end # SM
+		device pci 14.3 on
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end # LPC	0x790e
+		device pci 14.7 on  end # SD
+		device pci 18.0 on  end
+		device pci 18.1 on  end
+		device pci 18.2 on  end
+		device pci 18.3 on  end
+		device pci 18.4 on  end
+		device pci 18.5 on  end
+	end #domain
+end	#chip soc/amd/stoneyridge
diff --git a/src/mainboard/google/kahlee/variants/kahlee/gpio.c b/src/mainboard/google/kahlee/variants/kahlee/gpio.c
new file mode 100644
index 0000000000..e25f1a1e42
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/kahlee/gpio.c
@@ -0,0 +1,146 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <AGESA.h>
+#include <FchPlatform.h>
+#include <mainboard.h>
+#include <soc/smi.h>
+#include <soc/southbridge.h>
+#include <stdlib.h>
+#include <variant/gpio.h>
+
+const GPIO_CONTROL agesa_board_gpios[] = {
+	/* AGPIO2 PCIE/WLAN WAKE# SCI*/
+	{2, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+	/* SER TX */
+	{8, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+						| FCH_GPIO_OUTPUT_ENABLE},
+	/* SER RX */
+	{9, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+	/* AGPIO 12 */
+	{12, Function2, FCH_GPIO_PULL_UP_ENABLE },
+
+	/* TS_EN_SOC (TouchScreen enable GPIO) */
+	{13, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+						| FCH_GPIO_OUTPUT_ENABLE},
+
+	/* CAM_PWRON (Camera enable GPIO) */
+	{14, Function1,  FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+						| FCH_GPIO_OUTPUT_ENABLE},
+
+	/* EC_IN_RW */
+	{15, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+	/* APU_I2C_3_SCL */
+	{19, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+	/* APU_I2C_3_SDA */
+	{20, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+	/* AGPIO22 EC_SCI */
+	{22, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+	/* APU_BT_ON# */
+	{24, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+						| FCH_GPIO_OUTPUT_ENABLE},
+
+	/* DEVSLP1_SSD */
+	{67, Function1, FCH_GPIO_PULL_UP_ENABLE},
+
+	/* DEVSLP1_EMMC */
+	/* No Connect for now.
+	 * {70, Function1, FCH_GPIO_PULL_UP_ENABLE},
+	 */
+
+	/* SPI_TPM_CS_L */
+	{76, Function1, FCH_GPIO_PULL_DOWN_ENABLE | FCH_GPIO_OUTPUT_VALUE
+						  | FCH_GPIO_OUTPUT_ENABLE},
+
+	/* CAM_LED# */
+	{84, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+						| FCH_GPIO_OUTPUT_ENABLE},
+
+	/* TS_RST#  (TouchScreen Reset) */
+	{85, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+						| FCH_GPIO_OUTPUT_ENABLE},
+
+	/* WLAN_RST#_AUX */
+	{119, Function2, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE
+						 | FCH_GPIO_OUTPUT_ENABLE},
+
+	/* BD_ID1 */
+	{135, Function1, 0 },
+
+	/* TPM_SERIRQ# */
+	{139, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+	/* BD_ID2 */
+	{140, Function1, 0 },
+
+	/* APU_SPI_WP */
+	{142, Function1, FCH_GPIO_PULL_UP_ENABLE },
+
+	/* BD_ID3 */
+	{144, Function1, 0 },
+
+	{-1}
+};
+
+/*
+ * GPE setup table must match ACPI GPE ASL
+ *  { gevent, gpe, direction, level }
+ */
+static const struct sci_source gpe_table[] = {
+
+	/* EC AGPIO22/Gevent3 -> GPE 3 */
+	{
+		.scimap = 3,
+		.gpe = 3,
+		.direction = SMI_SCI_LVL_LOW,
+		.level = SMI_SCI_EDG,
+	},
+
+	/* PCIE/WLAN AGPIO2/Gevent8 -> GPE8 */
+	{
+		.scimap = 8,
+		.gpe = 8,
+		.direction = SMI_SCI_LVL_LOW,
+		.level = SMI_SCI_LVL,
+	},
+
+	/* EHCI USB_PME -> GPE24 */
+	{
+		.scimap = 24,
+		.gpe = 24,
+		.direction = SMI_SCI_LVL_HIGH,
+		.level = SMI_SCI_LVL,
+	},
+
+	/* XHCIC0 -> GPE31 */
+	{
+		.scimap = 56,
+		.gpe = 31,
+		.direction = SMI_SCI_LVL_HIGH,
+		.level = SMI_SCI_LVL,
+	},
+};
+
+const struct sci_source *get_gpe_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpe_table);
+	return gpe_table;
+}
diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/acpi/usb_oc.asl b/src/mainboard/google/kahlee/variants/kahlee/include/acpi/usb_oc.asl
new file mode 100644
index 0000000000..068d6fd96d
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/kahlee/include/acpi/usb_oc.asl
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* simple name description */
+/*
+ * DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
+ * {
+ *	#include "usb.asl"
+ * }
+ */
+
+/* USB overcurrent mapping pins.   */
+Name (UOM0, 0)
+Name (UOM1, 2)
+Name (UOM2, 0)
+Name (UOM3, 7)
+Name (UOM4, 2)
+Name (UOM5, 2)
+Name (UOM6, 6)
+Name (UOM7, 2)
+Name (UOM8, 6)
+Name (UOM9, 6)
+
+/* USB Overcurrent GPEs */
diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h
new file mode 100644
index 0000000000..dfb6354a3e
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __VARIANT_GPIO_H__
+#define __VARIANT_GPIO_H__
+
+#ifndef __ACPI__
+#include <soc/gpio.h>
+
+#define MEM_CONFIG0	GPIO_135
+#define MEM_CONFIG1	GPIO_140
+#define MEM_CONFIG2	GPIO_144
+
+/* SPI Write protect */
+#define CROS_WP_GPIO		GPIO_142
+#define GPIO_EC_IN_RW		GPIO_15
+
+#endif /* _ACPI__ */
+
+/* AGPIO22 -> GPE3 */
+#define EC_SCI_GPI		3
+
+/* TODO: Fix this */
+/* GPIO_S5_07 is EC_SMI#, but it is bit 23 in GPE_STS and ALT_GPIO_SMI. */
+#define EC_SMI_GPI		23
+
+#endif /* __VARIANT_GPIO_H__ */
diff --git a/src/mainboard/google/kahlee/variants/kahlee/memory.c b/src/mainboard/google/kahlee/variants/kahlee/memory.c
new file mode 100644
index 0000000000..4341b824b5
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/kahlee/memory.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <gpio.h> /* src/include/gpio.h */
+#include <baseboard/variants.h>
+#include <baseboard/gpio.h>
+
+size_t variant_board_id(void)
+{
+	gpio_t pads[] = {
+		[2] = MEM_CONFIG2,
+		[1] = MEM_CONFIG1,
+		[0] = MEM_CONFIG0,
+	};
+
+	return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads));
+}