mainboard/google/kahlee: create treeya variant

This is based on the grunt variant.

BUG=b:135551210
BRANCH=none
TEST=emerge-grunt coreboot chromeos-bootimage
Ensure that image-treeya.*.bin are created

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I40f3c9de87350777b02dd91d8c5b9dbe2eb9f6b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

10 files changed, 329 insertions, 0 deletions

diff --git a/src/mainboard/google/kahlee/variants/treeya/Makefile.inc b/src/mainboard/google/kahlee/variants/treeya/Makefile.inc
new file mode 100644
index 0000000000..0579e1899f
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/treeya/Makefile.inc
@@ -0,0 +1,20 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2017 Google, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+subdirs-y += ../baseboard/spd
+
+romstage-y += ../baseboard/romstage.c
+
+ramstage-y += ../baseboard/mainboard.c
diff --git a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb
new file mode 100644
index 0000000000..d73c47c6b8
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb
@@ -0,0 +1,170 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+chip soc/amd/stoneyridge
+	register "spd_addr_lookup" = "
+	{
+		{ {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0
+	}"
+	register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP"
+	register "uma_mode" = "UMAMODE_SPECIFIED_SIZE"
+	register "uma_size" = "16 * MiB"
+	register "stapm_percent" = "80"
+	register "stapm_time_ms" = "2500000"
+	register "stapm_power_mw" = "7800"
+
+	# Enable I2C0 for audio, USB3 hub at 400kHz
+	register "i2c[0]" = "{
+		.speed = I2C_SPEED_FAST,
+		.rise_time_ns = 95,
+		.fall_time_ns = 3,
+	}"
+
+	# Enable I2C1 for H1 at 400kHz
+	register "i2c[1]" = "{
+		.early_init = 1,
+		.speed = I2C_SPEED_FAST,
+		.rise_time_ns = 62,
+		.fall_time_ns = 2,
+	}"
+
+	# Enable I2C2 for trackpad, pen at 400kHz
+	register "i2c[2]" = "{
+		.speed = I2C_SPEED_FAST,
+		.rise_time_ns = 170,
+		.fall_time_ns = 91,
+	}"
+
+	# Enable I2C3 for touchscreen at 400kHz
+	register "i2c[3]" = "{
+		.speed = I2C_SPEED_FAST,
+		.rise_time_ns = 84,
+		.fall_time_ns = 50,
+	}"
+
+	register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \
+				    GPIO_I2C2_SCL | GPIO_I2C3_SCL"
+
+	device cpu_cluster 0 on
+		device lapic 10 on end
+	end
+	device domain 0 on
+		device pci 0.0 on  end # Root Complex
+		device pci 0.2 off end # IOMMU (Disabled for performance and battery)
+		device pci 1.0 on  end # Internal Graphics P2P bridge 0x98e4
+		device pci 1.1 on  end # Internal Multimedia
+		device pci 2.0 on  end # PCIe Host Bridge
+		device pci 2.1 on  end #
+		device pci 2.2 on  end #
+		device pci 2.3 on  end #
+		device pci 2.4 on
+			chip drivers/generic/bayhub
+				register "power_saving" = "1"
+				device pci 00.0 on end
+			end
+		end #
+		device pci 2.5 on  end #
+		device pci 8.0 on  end # PSP
+		device pci 9.0 on  end # PCIe Host Bridge
+		device pci 9.2 on  end # HDA
+		device pci 10.0 on  end # xHCI
+		device pci 11.0 off  end # SATA
+		device pci 12.0 on  end # EHCI
+		device pci 14.0 on      # SMbus
+		end # SMbus
+		device pci 14.3 on
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end # LPC
+		device pci 14.7 on  end # SD
+		device pci 18.0 on  end
+		device pci 18.1 on  end
+		device pci 18.2 on  end
+		device pci 18.3 on  end
+		device pci 18.4 on  end
+		device pci 18.5 on  end
+	end #domain
+	device mmio 0xfedc2000 on
+		chip drivers/generic/adau7002
+			device generic 0.0 on end
+		end
+		chip drivers/i2c/da7219
+			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_14)"
+			register "btn_cfg" = "50"
+			register "mic_det_thr" = "500"
+			register "jack_ins_deb" = "20"
+			register "jack_det_rate" = ""32ms_64ms""
+			register "jack_rem_deb" = "1"
+			register "a_d_btn_thr" = "0xa"
+			register "d_b_btn_thr" = "0x16"
+			register "b_c_btn_thr" = "0x21"
+			register "c_mic_btn_thr" = "0x3e"
+			register "btn_avg" = "4"
+			register "adc_1bit_rpt" = "1"
+			register "micbias_lvl" = "2600"
+			register "mic_amp_in_sel" = ""diff""
+			register "mclk_name" = ""oscout1""
+			device i2c 1a on end
+		end
+		chip drivers/generic/max98357a
+			register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_119)"
+			register "sdmode_delay" = "5"
+			device generic 0.1 on end
+		end
+	end
+	device mmio 0xfedc3000 on
+		chip drivers/i2c/tpm
+			register "hid" = ""GOOG0005""
+			register "desc" = ""Cr50 TPM""
+			register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)"
+			device i2c 50 on end
+		end
+	end
+	device mmio 0xfedc4000 on
+		chip drivers/i2c/generic
+			register "hid" = ""ELAN0000""
+			register "desc" = ""ELAN Touchpad""
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)"
+			register "wake" = "7"
+			device i2c 15 on end
+		end
+	end
+	device mmio 0xfedc5000 on
+		chip drivers/i2c/generic
+			register "hid" = ""RAYD0001""
+			register "desc" = ""Raydium Touchscreen""
+			register "probed" = "1"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)"
+			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)"
+			register "reset_delay_ms" = "20"
+			register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
+			register "enable_delay_ms" = "1"
+			register "has_power_resource" = "1"
+			device i2c 39 on end
+		end
+		chip drivers/i2c/generic
+			register "hid" = ""ELAN0001""
+			register "desc" = ""ELAN Touchscreen""
+			register "probed" = "1"
+			register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)"
+			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)"
+			register "reset_delay_ms" = "20"
+			register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
+			register "enable_delay_ms" = "1"
+			register "has_power_resource" = "1"
+			device i2c 10 on end
+		end
+	end
+end	#chip soc/amd/stoneyridge
diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/gpe.asl b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/gpe.asl
new file mode 100644
index 0000000000..0a08774206
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/gpe.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/acpi/gpe.asl>
diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/mainboard.asl
new file mode 100644
index 0000000000..4f91d72822
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/mainboard.asl
@@ -0,0 +1,17 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/acpi/mainboard.asl>
+#include <baseboard/acpi/audio.asl>
diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/routing.asl b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/routing.asl
new file mode 100644
index 0000000000..233494f51e
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/routing.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/acpi/routing.asl>
diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/sleep.asl b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/sleep.asl
new file mode 100644
index 0000000000..c5a1557962
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/sleep.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/acpi/sleep.asl>
diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/thermal.asl b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/thermal.asl
new file mode 100644
index 0000000000..77137bb903
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/thermal.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/acpi/thermal.asl>
diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h b/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h
new file mode 100644
index 0000000000..96388ae5e0
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h
@@ -0,0 +1,4 @@
+#include <baseboard/ec.h>
+
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/treeya/include/variant/gpio.h
new file mode 100644
index 0000000000..5a6b54044f
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/gpio.h
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/gpio.h>
diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/thermal.h b/src/mainboard/google/kahlee/variants/treeya/include/variant/thermal.h
new file mode 100644
index 0000000000..1bb78efa2a
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/thermal.h
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef THERMAL_H
+#define THERMAL_H
+
+/*
+ * Stoney Ridge Thermal Requirements 12 (6W)
+ * TDP (W) 6
+ * T die,max (°C) 95
+ * T ctl,max 85
+ * T die,lmt (default) 90
+ * T ctl,lmt (default) 80
+ */
+
+/* Control TDP Settings */
+#define CTL_TDP_SENSOR_ID		2	/* EC TIN2 */
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE		94
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE		85
+
+#endif