diff options
author | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-01-11 17:41:37 -0600 |
---|---|---|
committer | Martin L Roth <gaumless@gmail.com> | 2023-01-15 02:01:48 +0000 |
commit | 4902e9b35f1b62c2c28e582e33ad55d2543f1483 (patch) | |
tree | ecf83ae2983dbf3318bbb2bf315eee6cc3ed903d /src/mainboard/google/kahlee/variants | |
parent | 2e6c55946c4d4ff04e1bc8de7272a4cef63ed55d (diff) |
drivers/i2c/generic: Drop 'disable_gpio_export_in_crs' flag
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the
OS driver and ACPI thinking they own the GPIO. This can cause timing
problems because it's not clear which system should be controlling the
GPIO.
Previously, we flagged as an error any device which set the
'has_power_resource' flag but did not set 'disable_gpio_export_in_crs.'
There's no reason to require explicit disablement however, so drop the
superfluous 'disable' flag, and change the _CRS generation to check if
the GPIOs will be exported via the 'has_power_resource' flag instead.
BUG=b:265055477
TEST=build/boot skyrim, dump SSDT and verify touchscreen GPIOs only
listed under PRx, not under _CRS.
Change-Id: I837ae6c6fe4b8e1c4e10686406cba06bdb7759d2
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/mainboard/google/kahlee/variants')
6 files changed, 0 insertions, 11 deletions
diff --git a/src/mainboard/google/kahlee/variants/aleena/overridetree.cb b/src/mainboard/google/kahlee/variants/aleena/overridetree.cb index 9fb09b2ab3..c5d484bdc2 100644 --- a/src/mainboard/google/kahlee/variants/aleena/overridetree.cb +++ b/src/mainboard/google/kahlee/variants/aleena/overridetree.cb @@ -57,7 +57,6 @@ chip soc/amd/stoneyridge register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" register "enable_delay_ms" = "1" register "has_power_resource" = "1" - register "disable_gpio_export_in_crs" = "1" device i2c 39 on end end end diff --git a/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb index 86f589c30f..632ffa3e9a 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/baseboard/devicetree.cb @@ -94,7 +94,6 @@ chip soc/amd/stoneyridge register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" register "enable_delay_ms" = "1" register "has_power_resource" = "1" - register "disable_gpio_export_in_crs" = "1" device i2c 39 on end end chip drivers/i2c/generic @@ -107,7 +106,6 @@ chip soc/amd/stoneyridge register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" register "enable_delay_ms" = "1" register "has_power_resource" = "1" - register "disable_gpio_export_in_crs" = "1" device i2c 10 on end end end diff --git a/src/mainboard/google/kahlee/variants/careena/overridetree.cb b/src/mainboard/google/kahlee/variants/careena/overridetree.cb index 2067d38927..666373f1bc 100644 --- a/src/mainboard/google/kahlee/variants/careena/overridetree.cb +++ b/src/mainboard/google/kahlee/variants/careena/overridetree.cb @@ -66,7 +66,6 @@ chip soc/amd/stoneyridge register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" register "enable_delay_ms" = "1" register "has_power_resource" = "1" - register "disable_gpio_export_in_crs" = "1" device i2c 39 on end end chip drivers/i2c/hid @@ -79,7 +78,6 @@ chip soc/amd/stoneyridge register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" - register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 40 on end end diff --git a/src/mainboard/google/kahlee/variants/grunt/overridetree.cb b/src/mainboard/google/kahlee/variants/grunt/overridetree.cb index a8e599100e..0b155c5a7b 100644 --- a/src/mainboard/google/kahlee/variants/grunt/overridetree.cb +++ b/src/mainboard/google/kahlee/variants/grunt/overridetree.cb @@ -45,7 +45,6 @@ chip soc/amd/stoneyridge register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" register "enable_delay_ms" = "1" register "has_power_resource" = "1" - register "disable_gpio_export_in_crs" = "1" device i2c 39 on end end end diff --git a/src/mainboard/google/kahlee/variants/nuwani/overridetree.cb b/src/mainboard/google/kahlee/variants/nuwani/overridetree.cb index ce00674b45..74ab535ea3 100644 --- a/src/mainboard/google/kahlee/variants/nuwani/overridetree.cb +++ b/src/mainboard/google/kahlee/variants/nuwani/overridetree.cb @@ -69,7 +69,6 @@ chip soc/amd/stoneyridge register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" register "generic.reset_delay_ms" = "20" register "generic.has_power_resource" = "1" - register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end @@ -82,7 +81,6 @@ chip soc/amd/stoneyridge register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" register "generic.reset_delay_ms" = "45" register "generic.has_power_resource" = "1" - register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 20 on end end @@ -96,7 +94,6 @@ chip soc/amd/stoneyridge register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" register "enable_delay_ms" = "1" register "has_power_resource" = "1" - register "disable_gpio_export_in_crs" = "1" device i2c 39 on end end end diff --git a/src/mainboard/google/kahlee/variants/treeya/overridetree.cb b/src/mainboard/google/kahlee/variants/treeya/overridetree.cb index 9c4009e764..5c705246d8 100644 --- a/src/mainboard/google/kahlee/variants/treeya/overridetree.cb +++ b/src/mainboard/google/kahlee/variants/treeya/overridetree.cb @@ -86,7 +86,6 @@ chip soc/amd/stoneyridge register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" register "generic.reset_delay_ms" = "45" register "generic.has_power_resource" = "1" - register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 20 on end end @@ -100,7 +99,6 @@ chip soc/amd/stoneyridge register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" register "enable_delay_ms" = "1" register "has_power_resource" = "1" - register "disable_gpio_export_in_crs" = "1" device i2c 39 on end end end |