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authorMartin Roth <martinroth@google.com>2017-11-22 19:06:38 -0700
committerMartin Roth <martinroth@google.com>2017-11-28 00:59:53 +0000
commit320b41b148eecfd342e27ea250fbf73915f579bf (patch)
tree780fd08b30cbb79b40aa953289ad5ae8c9ad2a97 /src/mainboard/google/kahlee/chromeos.fmd
parent73031bcce071f6e760cc0655200dd3be2f39c8b7 (diff)
mainboard/google/kahlee: Update chromeos.fmd
- Remove SI_ALL section. This is no longer needed as the PSP dirctory is placed into the RO coreboot section. - Add 1MB Legacy section. - Add Memory cache section. These sections are called "MRC", which is an Intel term, but AMD platforms will use the same regions for saving the same sort of data. BUG=b:65497959, b:67035984 TEST=Build & boot kahlee Change-Id: I5e41a0aa6bd4b29b8014c6559126a29cd7ed45d8 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/mainboard/google/kahlee/chromeos.fmd')
-rw-r--r--src/mainboard/google/kahlee/chromeos.fmd39
1 files changed, 20 insertions, 19 deletions
diff --git a/src/mainboard/google/kahlee/chromeos.fmd b/src/mainboard/google/kahlee/chromeos.fmd
index af6dfc3ee0..82820984ea 100644
--- a/src/mainboard/google/kahlee/chromeos.fmd
+++ b/src/mainboard/google/kahlee/chromeos.fmd
@@ -1,37 +1,38 @@
-FLASH@0xff800000 0x800000 {
-SI_ALL@0x0 0xCB000 {
- UNUSED@0x00000 0x20000
- AMD_FW@0x20000 0xAB000
- }
-SI_BIOS@0xCB000 0x735000 {
- RW_SECTION_A@0x0 0x21e000 {
+FLASH@0xFF800000 0x800000 {
+ SI_BIOS@0x0 0x800000 {
+ RW_SECTION_A@0x0 0x21E000 {
VBLOCK_A@0x0 0x10000
FW_MAIN_A(CBFS)@0x10000 0x20DFC0
- RW_FWID_A@0x21dfc0 0x40
+ RW_FWID_A@0x21DFC0 0x40
}
- RW_SECTION_B@0x21e000 0x21e000 {
+ RW_SECTION_B@0x21E000 0x21E000 {
VBLOCK_B@0x0 0x10000
FW_MAIN_B(CBFS)@0x10000 0x20DFC0
- RW_FWID_B@0x21dfc0 0x40
+ RW_FWID_B@0x21DFC0 0x40
+ }
+ UNIFIED_MRC_CACHE@0x43C000 0x21000 {
+ RECOVERY_MRC_CACHE@0x0 0x10000
+ RW_MRC_CACHE@0x10000 0x10000
+ RW_VAR_MRC_CACHE@0x20000 0x1000
}
- RW_MRC_CACHE@0x43C000 0x10000
- RW_ELOG@0x44C000 0x4000
- RW_SHARED@0x450000 0x4000 {
+ RW_ELOG@0x45D000 0x4000
+
+ RW_SHARED@0x461000 0x4000 {
SHARED_DATA@0x0 0x2000
VBLOCK_DEV@0x2000 0x2000
}
- RW_VPD@0x454000 0x2000
- RW_UNUSED@0x456000 0x3F000
-# RW_LEGACY(CBFS)@0x200000 0x200000
- WP_RO@0x495000 0x2A0000{
+ RW_VPD@0x465000 0x2000
+ RW_LEGACY@0x467000 0x100000
+ RW_UNUSED@0x567000 0x8000
+ WP_RO@0x56F000 0x291000 {
RO_VPD@0x0 0x4000
RO_UNUSED@0x4000 0xc000
- RO_SECTION@0x10000 0x290000 {
+ RO_SECTION@0x10000 0x281000 {
FMAP@0x0 0x800
RO_FRID@0x800 0x40
RO_FRID_PAD@0x840 0x7c0
GBB@0x1000 0x70000
- COREBOOT(CBFS)@0x80000 0x210000
+ COREBOOT(CBFS)@0x71000 0x210000
}
}
}