diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2016-12-17 17:13:23 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-12-22 18:37:35 +0100 |
| commit | 0148fcb4e1d1c4e43cd21e7b28a65afd762daa6d (patch) | |
| tree | 2d89da8657235d12119187671564b294ed07b83b /src/mainboard/google/jecht | |
| parent | 6390e525fcbad63fbf4c0043ae248b24b9a9d0c6 (diff) | |
Combine Broadwell Chromeboxes using variant board scheme
Combine existing boards google/guado, rikku, and tidus using
their common reference board google/jecht as a base.
Additional changes besides simple consolidation include:
- simplify power LED functions
- simplify HDA verb definitions using azelia macros
- use common SoC functions to generate FADT table
- correct FADT table header version
- remove unused haswell_pci_irqs.asl
- remove unused header includes (various)
- set sane default fan speed (0x4d) for all variants
Variant setup modeled after google/beltino
Change-Id: I77a2dffe9601734916a33fd04ead98016ad0bc4b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17913
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/jecht')
34 files changed, 2079 insertions, 421 deletions
diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 8a30a4d963..37dac7e40c 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -1,7 +1,5 @@ -if BOARD_GOOGLE_JECHT - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y +config BOARD_GOOGLE_BASEBOARD_JECHT + def_bool n select SOC_INTEL_BROADWELL select BOARD_ROMSIZE_KB_8192 select SUPERIO_ITE_IT8772F @@ -11,7 +9,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select INTEL_INT15 + +if BOARD_GOOGLE_BASEBOARD_JECHT config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC @@ -23,9 +22,28 @@ config MAINBOARD_DIR string default google/jecht + +config VARIANT_DIR + string + default "guado" if BOARD_GOOGLE_GUADO + default "jecht" if BOARD_GOOGLE_JECHT + default "rikku" if BOARD_GOOGLE_RIKKU + default "tidus" if BOARD_GOOGLE_TIDUS + config MAINBOARD_PART_NUMBER string - default "Jecht" + default "Guado" if BOARD_GOOGLE_GUADO + default "Jecht" if BOARD_GOOGLE_JECHT + default "Rikku" if BOARD_GOOGLE_RIKKU + default "Tidus" if BOARD_GOOGLE_TIDUS + +config GBB_HWID + string + depends on CHROMEOS + default "GUADO TEST A-A 7416" if BOARD_GOOGLE_GUADO + default "JECHT TEST A-A 8958" if BOARD_GOOGLE_JECHT + default "RIKKU TEST A-A 0702" if BOARD_GOOGLE_RIKKU + default "TIDUS TEST A-A 0595" if BOARD_GOOGLE_TIDUS config MAX_CPUS int @@ -33,7 +51,7 @@ config MAX_CPUS config VGA_BIOS_FILE string - default "pci8086,0166.rom" + default "pci8086,0406.rom" config HAVE_IFD_BIN bool @@ -43,8 +61,4 @@ config HAVE_ME_BIN bool default n -config GBB_HWID - string - depends on CHROMEOS - default "JECHT TEST A-A 8958" endif diff --git a/src/mainboard/google/jecht/Kconfig.name b/src/mainboard/google/jecht/Kconfig.name index af806ee7f5..2a076547f5 100644 --- a/src/mainboard/google/jecht/Kconfig.name +++ b/src/mainboard/google/jecht/Kconfig.name @@ -1,2 +1,15 @@ +config BOARD_GOOGLE_GUADO + bool "Guado" + select BOARD_GOOGLE_BASEBOARD_JECHT + config BOARD_GOOGLE_JECHT bool "Jecht" + select BOARD_GOOGLE_BASEBOARD_JECHT + +config BOARD_GOOGLE_RIKKU + bool "Rikku" + select BOARD_GOOGLE_BASEBOARD_JECHT + +config BOARD_GOOGLE_TIDUS + bool "Tidus" + select BOARD_GOOGLE_BASEBOARD_JECHT diff --git a/src/mainboard/google/jecht/Makefile.inc b/src/mainboard/google/jecht/Makefile.inc index 0557cc27b7..4438ace885 100644 --- a/src/mainboard/google/jecht/Makefile.inc +++ b/src/mainboard/google/jecht/Makefile.inc @@ -18,7 +18,12 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += lan.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c led.c -romstage-y += pei_data.c -ramstage-y += pei_data.c +romstage-y += variants/$(VARIANT_DIR)/pei_data.c +ramstage-y += variants/$(VARIANT_DIR)/pei_data.c + +romstage-y += led.c + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
\ No newline at end of file diff --git a/src/mainboard/google/jecht/acpi/haswell_pci_irqs.asl b/src/mainboard/google/jecht/acpi/haswell_pci_irqs.asl deleted file mode 100644 index 40658a9839..0000000000 --- a/src/mainboard/google/jecht/acpi/haswell_pci_irqs.asl +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for IvyBridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, 0, 18 }, - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 22 }, - Package() { 0x001fffff, 1, 0, 18 }, - Package() { 0x001fffff, 2, 0, 17 }, - Package() { 0x001fffff, 3, 0, 16 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, 0, 20 }, - Package() { 0x0015ffff, 1, 0, 21 }, - Package() { 0x0015ffff, 2, 0, 21 }, - Package() { 0x0015ffff, 3, 0, 21 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, 0, 23 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - }) - } -} diff --git a/src/mainboard/google/jecht/acpi/mainboard.asl b/src/mainboard/google/jecht/acpi/mainboard.asl index b06944617b..16e63529d1 100644 --- a/src/mainboard/google/jecht/acpi/mainboard.asl +++ b/src/mainboard/google/jecht/acpi/mainboard.asl @@ -25,14 +25,6 @@ Scope (\_SB) } /* - * LPC Trusted Platform Module - */ -Scope (\_SB.PCI0.LPCB) -{ - #include <drivers/pc80/tpm/acpi/tpm.asl> -} - -/* * LAN connected to Root Port 3, becomes Root Port 1 after coalesce */ Scope (\_SB.PCI0.RP01) diff --git a/src/mainboard/google/jecht/acpi/superio.asl b/src/mainboard/google/jecht/acpi/superio.asl index 9b71632db8..1d3779216e 100644 --- a/src/mainboard/google/jecht/acpi/superio.asl +++ b/src/mainboard/google/jecht/acpi/superio.asl @@ -15,17 +15,17 @@ /* Values should match those defined in devicetree.cb */ -#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller -#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR +#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller +#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR -#undef SIO_ENABLE_PS2K // pnp 2e.5: Disable PS/2 Keyboard -#undef SIO_ENABLE_PS2M // pnp 2e.6: Disable PS/2 Mouse -#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1 -#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller -#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60 -#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62 -#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO -#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 -#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 +#undef SIO_ENABLE_PS2K // pnp 2e.5: Disable PS/2 Keyboard +#undef SIO_ENABLE_PS2M // pnp 2e.6: Disable PS/2 Mouse +#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1 +#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller +#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60 +#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62 +#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO +#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 +#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 #include "superio/ite/it8772f/acpi/superio.asl" diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c index 655acc6ea6..0c6a37222d 100644 --- a/src/mainboard/google/jecht/acpi_tables.c +++ b/src/mainboard/google/jecht/acpi_tables.c @@ -26,7 +26,17 @@ #include <device/pci_ids.h> #include <soc/acpi.h> #include <soc/nvs.h> -#include "thermal.h" +#include <variant/thermal.h> + + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tmps = TEMPERATURE_SENSOR_ID; + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tmax = MAX_TEMPERATURE; + gnvs->flvl = 1; +} void acpi_create_gnvs(global_nvs_t *gnvs) { @@ -38,10 +48,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs) /* Disable USB ports in S5 */ gnvs->s5u0 = 0; - gnvs->tmps = TEMPERATURE_SENSOR_ID; - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; - gnvs->tmax = MAX_TEMPERATURE; + acpi_update_thermal_table(gnvs); } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index 4d16ed694f..8a2129f4eb 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -9,9 +9,6 @@ chip soc/intel/broadwell # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - - - register "pirqa_routing" = "0x8b" register "pirqb_routing" = "0x8a" register "pirqc_routing" = "0x8b" @@ -84,8 +81,14 @@ chip soc/intel/broadwell register "skip_keyboard" = "1" # Enable PECI on TMPIN3 register "peci_tmpin" = "3" + # Disable use of TMPIN1 + register "tmpin1_mode" = "0" + # Enable Thermal Diode on TMPIN2 + register "tmpin2_mode" = "1" # Enable FAN2 register "fan2_enable" = "1" + # Default FAN2 speed + register "fan2_speed" = "0x4d" device pnp 2e.0 off end # FDC device pnp 2e.1 on # Serial Port 1 diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl index 3132aab20a..1ac32887d1 100644 --- a/src/mainboard/google/jecht/dsdt.asl +++ b/src/mainboard/google/jecht/dsdt.asl @@ -44,7 +44,7 @@ DefinitionBlock( } // Thermal handler - #include "acpi/thermal.asl" + #include <variant/acpi/thermal.asl> // Chrome OS specific #include <vendorcode/google/chromeos/acpi/chromeos.asl> diff --git a/src/mainboard/google/jecht/fadt.c b/src/mainboard/google/jecht/fadt.c index c377d6745d..70fd2ceb1e 100644 --- a/src/mainboard/google/jecht/fadt.c +++ b/src/mainboard/google/jecht/fadt.c @@ -15,21 +15,16 @@ */ #include <string.h> -#include <device/pci.h> #include <soc/acpi.h> -#include <cpu/x86/smm.h> -#include <soc/pch.h> -#include <soc/iomap.h> -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - u16 pmbase = ACPI_BASE_ADDRESS; memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = 5; + header->revision = 3; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); @@ -40,114 +35,12 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->model = 1; fadt->preferred_pm_profile = PM_MOBILE; - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x80; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 32; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; fadt->x_firmware_ctl_l = (unsigned long)facs; fadt->x_firmware_ctl_h = 0; fadt->x_dsdt_l = (unsigned long)dsdt; fadt->x_dsdt_h = 0; - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 0; - fadt->x_gpe0_blk.bit_width = 0; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = 0; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_in_fadt(fadt); header->checksum = acpi_checksum((void *) fadt, header->length); diff --git a/src/mainboard/google/jecht/hda_verb.c b/src/mainboard/google/jecht/hda_verb.c index 284015de6d..01ba78f34b 100644 --- a/src/mainboard/google/jecht/hda_verb.c +++ b/src/mainboard/google/jecht/hda_verb.c @@ -19,75 +19,59 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 0x10ec0283, // Subsystem ID - 0x0000000c, // Number of jacks (NID entries) + 0x0000000e, // Number of jacks (NID entries) - /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */ - 0x00172083, - 0x00172102, - 0x001722ec, - 0x00172310, + 0x0017ff00, // Function Reset + 0x0017ff00, // Double Function Reset + 0x000F0000, // Pad - get vendor id + 0x000F0002, // Pad - get revision id + + /* NID 0x01, HDA Codec Subsystem ID Verb Table */ + AZALIA_SUBVENDOR(0x0, 0x11790670), /* Pin Widget Verb Table */ - /* Pin Complex (NID 0x12) DMIC */ - 0x01271cf0, - 0x01271d11, - 0x01271e11, - 0x01271f41, - - /* Pin Complex (NID 0x14) SPKR-OUT PORTD */ - 0x01471cf0, - 0x01471d11, - 0x01471e11, - 0x01471f40, - - /* Pin Complex (NID 0x17) */ - 0x01771cf0, - 0x01771d11, - 0x01771e11, - 0x01771f41, - - /* Pin Complex (NID 0x18) MIC1 PORTB */ - 0x01971c11, // group 1, cap 1 - 0x01971d10, // black, jack detect - 0x01971ea7, // mic in, analog - 0x01971f03, // connector, left panel - - /* Pin Complex (NID 0x19) MIC2 PORTF */ - 0x01871cf0, - 0x01871d11, - 0x01871e11, - 0x01871f41, - - /* Pin Complex (NID 0x1A) LINE1 PORTC */ - 0x01a71cf0, - 0x01a71d11, - 0x01a71e11, - 0x01a71f41, - - /* Pin Complex (NID 0x1B) LINE2 PORTE */ - 0x01a71cf0, - 0x01a71d11, - 0x01a71e11, - 0x01a71f41, - - /* Pin Complex (NID 0x1d) PCBeep */ - 0x01d71c2d, // eapd low on ex-amp, laptop, custom enable - 0x01d71d81, // mute spkr on hpout - 0x01d71e15, // pcbeep en able, checksum - 0x01d71f40, // no physical, internal - - /* Pin Complex (NID 0x1E) SPDIF-OUT */ - 0x01e71cf0, - 0x01e71d11, - 0x01e71e11, - 0x01e71f41, + /* Pin Complex (NID 0x12) DMIC - Disabled */ + AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), + + /* Pin Complex (NID 0x14) SPKR-OUT PORTD - Disabled */ + AZALIA_PIN_CFG(0x0, 0x14, 0x411111f0), + + /* Pin Complex (NID 0x17) MONO Out - Disabled */ + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + + /* Pin Complex (NID 0x18) MIC1 PORTB */ + // group 1, cap 1 + // black, jack detect + // mic in, analog + // connector, left panel + AZALIA_PIN_CFG(0x0, 0x18, 0x03a71011), + + /* Pin Complex (NID 0x19) MIC2 PORTF - Disabled */ + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + + /* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */ + AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0), + + /* Pin Complex (NID 0x1B) LINE2 PORTE - Disabled */ + AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0), + + /* Pin Complex (NID 0x1D) PCBeep */ + // eapd low on ex-amp, laptop, custom enable + // mute spkr on hpout + // pcbeep en able, checksum + // no physical, internal + AZALIA_PIN_CFG(0x0, 0x1D, 0x4015812d), + + /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled */ + AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0), /* Pin Complex (NID 0x21) HPOUT PORT-I */ - 0x02171c1f, // group1, - 0x02171d10, // black, jack detect - 0x02171e21, // HPOut, 1/8 stereo - 0x02171f03, // connector, left panel + // group1, + // black, jack detect + // HPOut, 1/8 stereo + // connector, left panel + AZALIA_PIN_CFG(0x0, 0x21, 0x0321101f), /* Undocumented settings from Realtek (needed for beep_gen) */ /* Widget node 0x20 */ @@ -95,6 +79,12 @@ const u32 cim_verb_data[] = { 0x02040c20, 0x0205001b, 0x0204081b, + + /* Tuned jack detection */ + 0x02050043, + 0x0204A614, + 0x02050047, + 0x02049470, }; const u32 pc_beep_verbs[] = { diff --git a/src/mainboard/google/jecht/lan.c b/src/mainboard/google/jecht/lan.c index bb6ff6e016..59ed1114a7 100644 --- a/src/mainboard/google/jecht/lan.c +++ b/src/mainboard/google/jecht/lan.c @@ -21,7 +21,7 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <southbridge/intel/bd82x6x/pch.h> +#include <soc/pch.h> #include "onboard.h" static unsigned int search(char *p, u8 *a, unsigned int lengthp, diff --git a/src/mainboard/google/jecht/led.c b/src/mainboard/google/jecht/led.c new file mode 100644 index 0000000000..50cf32e3e1 --- /dev/null +++ b/src/mainboard/google/jecht/led.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <superio/ite/it8772f/it8772f.h> +#include "onboard.h" + +void set_power_led(int state) +{ + it8772f_gpio_led(IT8772F_GPIO_DEV, + 1, /* set */ + 0x01, /* select */ + state == LED_OFF ? 0x00 : 0x01, /* polarity */ + state == LED_BLINK ? 0x01 : 0x00, /* pullup/pulldown */ + 0x01, /* output */ + state == LED_BLINK ? 0x00 : 0x01, /* I/O function */ + SIO_GPIO_BLINK_GPIO10, + IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); +} diff --git a/src/mainboard/google/jecht/mainboard.c b/src/mainboard/google/jecht/mainboard.c index cacf0e71a8..7e57505426 100644 --- a/src/mainboard/google/jecht/mainboard.c +++ b/src/mainboard/google/jecht/mainboard.c @@ -14,22 +14,8 @@ * GNU General Public License for more details. */ -#include <types.h> -#include <string.h> -#include <smbios.h> -#include <device/device.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <console/console.h> -#if CONFIG_VGA_ROM_RUN -#include <x86emu/x86emu.h> -#endif -#include <pc80/mc146818rtc.h> #include <arch/acpi.h> #include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> #include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h" @@ -39,92 +25,6 @@ void mainboard_suspend_resume(void) outb(0xcb, 0xb2); } -#if CONFIG_VGA_ROM_RUN -static int int15_handler(void) -{ - int res = 0; - - printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", - __func__, X86_AX, X86_BX, X86_CX, X86_DX); - - switch (X86_AX) { - case 0x5f34: - /* - * Set Panel Fitting Hook: - * bit 2 = Graphics Stretching - * bit 1 = Text Stretching - * bit 0 = Centering (do not set with bit1 or bit2) - * 0 = video bios default - */ - X86_AX = 0x005f; - X86_CX = 0x0001; - res = 1; - break; - case 0x5f35: - /* - * Boot Display Device Hook: - * bit 0 = CRT - * bit 1 = TV (eDP) * - * bit 2 = EFP * - * bit 3 = LFP - * bit 4 = CRT2 - * bit 5 = TV2 (eDP) * - * bit 6 = EFP2 * - * bit 7 = LFP2 - */ - X86_AX = 0x005f; - X86_CX = 0x0000; - res = 1; - break; - case 0x5f51: - /* - * Hook to select active LFP configuration: - * 00h = No LVDS, VBIOS does not enable LVDS - * 01h = Int-LVDS, LFP driven by integrated LVDS decoder - * 02h = SVDO-LVDS, LFP driven by SVDO decoder - * 03h = eDP, LFP Driven by Int-DisplayPort encoder - */ - X86_AX = 0x005f; - X86_CX = 0x0003; - res = 1; - break; - case 0x5f70: - switch ((X86_CX >> 8) & 0xff) { - case 0: - /* Get Mux */ - X86_AX = 0x005f; - X86_CX = 0x0000; - res = 1; - break; - case 1: - /* Set Mux */ - X86_AX = 0x005f; - X86_CX = 0x0000; - res = 1; - break; - case 2: - /* Get SG/Non-SG mode */ - X86_AX = 0x005f; - X86_CX = 0x0000; - res = 1; - break; - default: - /* Interrupt was not handled */ - printk(BIOS_DEBUG, - "Unknown INT15 5f70 function: 0x%02x\n", - ((X86_CX >> 8) & 0xff)); - break; - } - break; - - default: - printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); - break; - } - return res; -} -#endif - static void mainboard_init(device_t dev) { lan_init(); @@ -137,10 +37,6 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; -#if CONFIG_VGA_ROM_RUN - /* Install custom int15 handler for VGA OPROM */ - mainboard_interrupt_handlers(0x15, &int15_handler); -#endif } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/jecht/onboard.h b/src/mainboard/google/jecht/onboard.h index f5212d033d..96c792c58a 100644 --- a/src/mainboard/google/jecht/onboard.h +++ b/src/mainboard/google/jecht/onboard.h @@ -18,6 +18,14 @@ #ifndef __ACPI__ void lan_init(void); + +void set_power_led(int state); + +enum { + LED_OFF = 0, + LED_ON, + LED_BLINK, +}; #endif /* defines for programming the MAC address */ @@ -33,4 +41,13 @@ void lan_init(void); /* WLAN wake is GPIO 10 */ #define JECHT_WLAN_WAKE_GPIO 10 +/* USB Charger Control: GPIO26 */ +#define GPIO_USB_CTL_1 26 + +/* IT8772F defs */ +#define IT8772F_BASE 0x2e +#define IT8772F_SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1) +#define IT8772F_GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO) +#define IT8772F_DUMMY_DEV PNP_DEV(IT8772F_BASE, 0) + #endif diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c index 2d19b26d62..a71d3fe53c 100644 --- a/src/mainboard/google/jecht/romstage.c +++ b/src/mainboard/google/jecht/romstage.c @@ -25,11 +25,9 @@ #include <superio/ite/common/ite.h> #include <superio/ite/it8772f/it8772f.h> #include <mainboard/google/jecht/spd/spd.h> -#include "gpio.h" +#include <variant/gpio.h> +#include "onboard.h" -#define DUMMY_DEV PNP_DEV(0x2e, 0) -#define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) void mainboard_romstage_entry(struct romstage_params *rp) { @@ -53,7 +51,11 @@ void mainboard_romstage_entry(struct romstage_params *rp) void mainboard_pre_console_init(void) { /* Early SuperIO setup */ - it8772f_ac_resume_southbridge(DUMMY_DEV); - ite_kill_watchdog(GPIO_DEV); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + it8772f_ac_resume_southbridge(IT8772F_DUMMY_DEV); + ite_kill_watchdog(IT8772F_GPIO_DEV); + ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Turn On Power LED */ + set_power_led(LED_ON); + } diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c index 3b47ac6454..8243354299 100644 --- a/src/mainboard/google/jecht/smihandler.c +++ b/src/mainboard/google/jecht/smihandler.c @@ -27,6 +27,7 @@ #include <soc/nvs.h> #include <soc/pm.h> #include <soc/smm.h> +#include "onboard.h" int mainboard_io_trap_handler(int smif) { @@ -58,8 +59,15 @@ void mainboard_smi_sleep(u8 slp_typ) /* Disable USB charging if required */ switch (slp_typ) { case ACPI_S3: + set_power_led(LED_BLINK); + + /* Enable DCP mode */ + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_TIDUS)) { + set_gpio(GPIO_USB_CTL_1, 0); + } break; case ACPI_S5: + set_power_led(LED_OFF); break; } } diff --git a/src/mainboard/google/jecht/spd/spd.c b/src/mainboard/google/jecht/spd/spd.c index 407dd7f5a9..25409644d3 100644 --- a/src/mainboard/google/jecht/spd/spd.c +++ b/src/mainboard/google/jecht/spd/spd.c @@ -13,13 +13,7 @@ * GNU General Public License for more details. */ -#include <cbfs.h> -#include <console/console.h> -#include <endian.h> -#include <string.h> -#include <soc/gpio.h> #include <soc/pei_data.h> -#include <soc/romstage.h> #include <mainboard/google/jecht/spd/spd.h> /* Copy SPD data for on-board memory */ diff --git a/src/mainboard/google/jecht/acpi/thermal.asl b/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl index e686eab96e..1cd1b9b713 100644 --- a/src/mainboard/google/jecht/acpi/thermal.asl +++ b/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl @@ -154,9 +154,9 @@ Scope (\_TZ) Method (_AC4) { If (LLessEqual (\FLVL, 4)) { - Return (CTOK (FAN4_THRESHOLD_OFF)) + Return (CTOK (0)) } Else { - Return (CTOK (FAN4_THRESHOLD_ON)) + Return (CTOK (0)) } } diff --git a/src/mainboard/google/jecht/variants/guado/include/variant/gpio.h b/src/mainboard/google/jecht/variants/guado/include/variant/gpio.h new file mode 100644 index 0000000000..4c167e3a58 --- /dev/null +++ b/src/mainboard/google/jecht/variants/guado/include/variant/gpio.h @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef GUADO_GPIO_H +#define GUADO_GPIO_H + +#include <soc/gpio.h> + +static const struct gpio_config mainboard_gpio_config[] = { + PCH_GPIO_UNUSED, /* 0: UNUSED */ + PCH_GPIO_UNUSED, /* 1: UNUSED */ + PCH_GPIO_UNUSED, /* 2: UNUSED */ + PCH_GPIO_UNUSED, /* 3: UNUSED */ + PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ + PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ + PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ + PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ + PCH_GPIO_ACPI_SCI, /* 8: LAN_WAKE_L_Q */ + PCH_GPIO_OUT_HIGH, /* 9: PP3300_WLAN_EN */ + PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ + PCH_GPIO_UNUSED, /* 11: SMBALERT */ + PCH_GPIO_INPUT_INVERT, /* 12: RECOVERY_L */ + PCH_GPIO_UNUSED, /* 13: UNUSED */ + PCH_GPIO_UNUSED, /* 14: UNUSED */ + PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 16: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 17: PP3300_VP8_EN */ + PCH_GPIO_UNUSED, /* 18: UNUSED */ + PCH_GPIO_UNUSED, /* 19: UNUSED */ + PCH_GPIO_NATIVE, /* 20: NATIVE: CLK_PCIE_REQ2# */ + PCH_GPIO_NATIVE, /* 21: NATIVE: CLK_PCIE_REQ3# */ + PCH_GPIO_NATIVE, /* 22: NATIVE: CLK_PCIE_REQ4# */ + PCH_GPIO_UNUSED, /* 23: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 24: WLAN_OFF_L */ + PCH_GPIO_UNUSED, /* 25: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 26: USB_CTL_1 */ + PCH_GPIO_UNUSED, /* 27: UNUSED */ + PCH_GPIO_OUT_LOW, /* 28: USB_ILIM_SEL */ + PCH_GPIO_UNUSED, /* 29: UNUSED */ + PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSPWRACK_L */ + PCH_GPIO_NATIVE, /* 31: NATIVE: PCH_ACPRESENT */ + PCH_GPIO_NATIVE, /* 32: NATIVE: CLKRUN# */ + PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ + PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ + PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ + PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ + PCH_GPIO_UNUSED, /* 37: UNUSED */ + PCH_GPIO_UNUSED, /* 38: UNUSED */ + PCH_GPIO_UNUSED, /* 39: UNUSED */ + PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ + PCH_GPIO_NATIVE, /* 41: NATIVE: USB_OC1# */ + PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ + PCH_GPIO_NATIVE, /* 43: NATIVE: USB_OC3# */ + PCH_GPIO_UNUSED, /* 44: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 45: PP5000_CODEC_EN */ + PCH_GPIO_OUT_HIGH, /* 46: BT_DISABLE_L */ + PCH_GPIO_OUT_HIGH, /* 47: USB1_PWR_EN */ + PCH_GPIO_UNUSED, /* 48: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 49: POWER_LED */ + PCH_GPIO_OUT_HIGH, /* 50: VP8_DISABLE_L */ + PCH_GPIO_UNUSED, /* 51: UNUSED */ + PCH_GPIO_UNUSED, /* 52: UNUSED */ + PCH_GPIO_UNUSED, /* 53: UNUSED */ + PCH_GPIO_UNUSED, /* 54: UNUSED */ + PCH_GPIO_UNUSED, /* 55: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 56: USB2_PWR_EN */ + PCH_GPIO_OUT_HIGH, /* 57: USB3_PWR_EN */ + PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ + PCH_GPIO_OUT_HIGH, /* 59: PP3300_LAN_EN */ + PCH_GPIO_NATIVE, /* 60: NATIVE: SMB0ALERT# */ + PCH_GPIO_UNUSED, /* 61: UNUSED */ + PCH_GPIO_UNUSED, /* 62: UNUSED */ + PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ + PCH_GPIO_UNUSED, /* 64: UNUSED */ + PCH_GPIO_UNUSED, /* 65: UNUSED */ + PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 67: UNUSED */ + PCH_GPIO_UNUSED, /* 68: UNUSED */ + PCH_GPIO_UNUSED, /* 69: UNUSED */ + PCH_GPIO_UNUSED, /* 70: UNUSED */ + PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ + PCH_GPIO_UNUSED, /* 72: UNUSED */ + PCH_GPIO_UNUSED, /* 73: UNUSED */ + PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ + PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ + PCH_GPIO_UNUSED, /* 76: UNUSED */ + PCH_GPIO_UNUSED, /* 77: UNUSED */ + PCH_GPIO_UNUSED, /* 78: UNUSED */ + PCH_GPIO_UNUSED, /* 79: UNUSED */ + PCH_GPIO_UNUSED, /* 80: UNUSED */ + PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */ + PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ + PCH_GPIO_UNUSED, /* 83: UNUSED */ + PCH_GPIO_UNUSED, /* 84: UNUSED */ + PCH_GPIO_UNUSED, /* 85: UNUSED */ + PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 87: UNUSED */ + PCH_GPIO_UNUSED, /* 88: UNUSED */ + PCH_GPIO_UNUSED, /* 89: UNUSED */ + PCH_GPIO_UNUSED, /* 90: UNUSED */ + PCH_GPIO_UNUSED, /* 91: UNUSED */ + PCH_GPIO_UNUSED, /* 92: UNUSED */ + PCH_GPIO_UNUSED, /* 93: UNUSED */ + PCH_GPIO_UNUSED, /* 94: UNUSED */ + PCH_GPIO_END +}; + +#endif diff --git a/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h b/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h new file mode 100644 index 0000000000..d299b14d08 --- /dev/null +++ b/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef THERMAL_H +#define THERMAL_H + +#define TEMPERATURE_SENSOR_ID 0 /* PECI */ + +/* Fan is at default speed */ +#define FAN4_PWM 0x4d + +/* Fan is at LOW speed */ +#define FAN3_THRESHOLD_OFF 40 +#define FAN3_THRESHOLD_ON 50 +#define FAN3_PWM 0x55 + +/* Fan is at MEDIUM speed */ +#define FAN2_THRESHOLD_OFF 55 +#define FAN2_THRESHOLD_ON 67 +#define FAN2_PWM 0xa6 + +/* Fan is at HIGH speed */ +#define FAN1_THRESHOLD_OFF 65 +#define FAN1_THRESHOLD_ON 70 +#define FAN1_PWM 0xc0 + +/* Fan is at FULL speed */ +#define FAN0_THRESHOLD_OFF 90 +#define FAN0_THRESHOLD_ON 100 +#define FAN0_PWM 0xff + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 104 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 95 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 105 + +#endif diff --git a/src/mainboard/google/jecht/pei_data.c b/src/mainboard/google/jecht/variants/guado/pei_data.c index 1b5ea51532..1b5ea51532 100644 --- a/src/mainboard/google/jecht/pei_data.c +++ b/src/mainboard/google/jecht/variants/guado/pei_data.c diff --git a/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl new file mode 100644 index 0000000000..1cd1b9b713 --- /dev/null +++ b/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl @@ -0,0 +1,339 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../thermal.h" + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 2 seconds + Name (_TSP, 20) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + // Start fan at state 4 = lowest temp state + Method (_INI) + { + Store (4, \FLVL) + Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + + Method (TCHK, 0, Serialized) + { + // Get CPU Temperature from PECI via SuperIO TMPIN3 + Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) + + // Check for "no reading available + If (LEqual (Local0, 0x80)) { + Return (CTOK (FAN0_THRESHOLD_ON)) + } + + // Check for invalid readings + If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + Return (CTOK (FAN0_THRESHOLD_ON)) + } + + // PECI raw value is an offset from Tj_max + Subtract (255, Local0, Local1) + + // Handle values greater than Tj_max + If (LGreaterEqual (Local1, \TMAX)) { + Return (CTOK (\TMAX)) + } + + // Subtract from Tj_max to get temperature + Subtract (\TMAX, Local1, Local0) + Return (CTOK (Local0)) + } + + Method (_TMP, 0, Serialized) + { + // Get temperature from SuperIO in deci-kelvin + Store (TCHK (), Local0) + + // Critical temperature in deci-kelvin + Store (CTOK (\TMAX), Local1) + + If (LGreaterEqual (Local0, Local1)) { + Store ("CRITICAL TEMPERATURE", Debug) + Store (Local0, Debug) + + // Wait 1 second for SuperIO to re-poll + Sleep (1000) + + // Re-read temperature from SuperIO + Store (TCHK (), Local0) + + Store ("RE-READ TEMPERATURE", Debug) + Store (Local0, Debug) + } + + Return (Local0) + } + + Method (_AC0) { + If (LLessEqual (\FLVL, 0)) { + Return (CTOK (FAN0_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN0_THRESHOLD_ON)) + } + } + + Method (_AC1) { + If (LLessEqual (\FLVL, 1)) { + Return (CTOK (FAN1_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN1_THRESHOLD_ON)) + } + } + + Method (_AC2) { + If (LLessEqual (\FLVL, 2)) { + Return (CTOK (FAN2_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN2_THRESHOLD_ON)) + } + } + + Method (_AC3) { + If (LLessEqual (\FLVL, 3)) { + Return (CTOK (FAN3_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN3_THRESHOLD_ON)) + } + } + + Method (_AC4) { + If (LLessEqual (\FLVL, 4)) { + Return (CTOK (0)) + } Else { + Return (CTOK (0)) + } + } + + Name (_AL0, Package () { FAN0 }) + Name (_AL1, Package () { FAN1 }) + Name (_AL2, Package () { FAN2 }) + Name (_AL3, Package () { FAN3 }) + Name (_AL4, Package () { FAN4 }) + + PowerResource (FNP0, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 0)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (0, \FLVL) + Store (FAN0_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (1, \FLVL) + Store (FAN1_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP1, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 1)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (1, \FLVL) + Store (FAN1_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (2, \FLVL) + Store (FAN2_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP2, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 2)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (2, \FLVL) + Store (FAN2_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (3, \FLVL) + Store (FAN3_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP3, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 3)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (3, \FLVL) + Store (FAN3_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (4, \FLVL) + Store (FAN4_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP4, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 4)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (4, \FLVL) + Store (FAN4_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (4, \FLVL) + Store (FAN4_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + Device (FAN0) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 0) + Name (_PR0, Package () { FNP0 }) + } + + Device (FAN1) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 1) + Name (_PR0, Package () { FNP1 }) + } + + Device (FAN2) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 2) + Name (_PR0, Package () { FNP2 }) + } + + Device (FAN3) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 3) + Name (_PR0, Package () { FNP3 }) + } + + Device (FAN4) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 4) + Name (_PR0, Package () { FNP4 }) + } + } +} diff --git a/src/mainboard/google/jecht/gpio.h b/src/mainboard/google/jecht/variants/jecht/include/variant/gpio.h index 94e6516ce7..94e6516ce7 100644 --- a/src/mainboard/google/jecht/gpio.h +++ b/src/mainboard/google/jecht/variants/jecht/include/variant/gpio.h diff --git a/src/mainboard/google/jecht/thermal.h b/src/mainboard/google/jecht/variants/jecht/include/variant/thermal.h index 3e8a7da595..29559eb754 100644 --- a/src/mainboard/google/jecht/thermal.h +++ b/src/mainboard/google/jecht/variants/jecht/include/variant/thermal.h @@ -18,10 +18,8 @@ #define TEMPERATURE_SENSOR_ID 0 /* PECI */ -/* Fan is OFF */ -#define FAN4_THRESHOLD_OFF 0 -#define FAN4_THRESHOLD_ON 0 -#define FAN4_PWM 0x00 +/* Fan is at default speed */ +#define FAN4_PWM 0x4d /* Fan is at LOW speed */ #define FAN3_THRESHOLD_OFF 50 diff --git a/src/mainboard/google/jecht/variants/jecht/pei_data.c b/src/mainboard/google/jecht/variants/jecht/pei_data.c new file mode 100644 index 0000000000..1b5ea51532 --- /dev/null +++ b/src/mainboard/google/jecht/variants/jecht/pei_data.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->ec_present = 0; + + /* P0: VP8 */ + pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0, + USB_PORT_MINI_PCIE); + /* P1: Port A, CN22 */ + pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, + USB_PORT_INTERNAL); + /* P2: Port B, CN23 */ + pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1, + USB_PORT_INTERNAL); + /* P3: WLAN */ + pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_MINI_PCIE); + /* P4: Port C, CN25 */ + pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, + USB_PORT_INTERNAL); + /* P5: Port D, CN25 */ + pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2, + USB_PORT_INTERNAL); + /* P6: Card Reader */ + pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_INTERNAL); + /* P7: EMPTY */ + pei_data_usb2_port(pei_data, 7, 0x0000, 0, 0, + USB_PORT_SKIP); + + /* P1: CN22 */ + pei_data_usb3_port(pei_data, 0, 1, 0, 0); + /* P2: CN23 */ + pei_data_usb3_port(pei_data, 1, 1, 1, 0); + /* P3: CN25 */ + pei_data_usb3_port(pei_data, 2, 1, 2, 0); + /* P4: CN25 */ + pei_data_usb3_port(pei_data, 3, 1, 2, 0); +} diff --git a/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl new file mode 100644 index 0000000000..151ac51289 --- /dev/null +++ b/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl @@ -0,0 +1,339 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../thermal.h" + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 2 seconds + Name (_TSP, 20) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + // Start fan at state 4 = lowest temp state + Method (_INI) + { + Store (4, \FLVL) + Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + + Method (TCHK, 0, Serialized) + { + // Get CPU Temperature from PECI via SuperIO TMPIN3 + Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) + + // Check for "no reading available + If (LEqual (Local0, 0x80)) { + Return (CTOK (FAN0_THRESHOLD_ON)) + } + + // Check for invalid readings + If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + Return (CTOK (FAN0_THRESHOLD_ON)) + } + + // PECI raw value is an offset from Tj_max + Subtract (255, Local0, Local1) + + // Handle values greater than Tj_max + If (LGreaterEqual (Local1, \TMAX)) { + Return (CTOK (\TMAX)) + } + + // Subtract from Tj_max to get temperature + Subtract (\TMAX, Local1, Local0) + Return (CTOK (Local0)) + } + + Method (_TMP, 0, Serialized) + { + // Get temperature from SuperIO in deci-kelvin + Store (TCHK (), Local0) + + // Critical temperature in deci-kelvin + Store (CTOK (\TMAX), Local1) + + If (LGreaterEqual (Local0, Local1)) { + Store ("CRITICAL TEMPERATURE", Debug) + Store (Local0, Debug) + + // Wait 1 second for SuperIO to re-poll + Sleep (1000) + + // Re-read temperature from SuperIO + Store (TCHK (), Local0) + + Store ("RE-READ TEMPERATURE", Debug) + Store (Local0, Debug) + } + + Return (Local0) + } + + Method (_AC0) { + If (LLessEqual (\FLVL, 0)) { + Return (CTOK (FAN0_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN0_THRESHOLD_ON)) + } + } + + Method (_AC1) { + If (LLessEqual (\FLVL, 1)) { + Return (CTOK (FAN1_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN1_THRESHOLD_ON)) + } + } + + Method (_AC2) { + If (LLessEqual (\FLVL, 2)) { + Return (CTOK (FAN2_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN2_THRESHOLD_ON)) + } + } + + Method (_AC3) { + If (LLessEqual (\FLVL, 3)) { + Return (CTOK (FAN3_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN3_THRESHOLD_ON)) + } + } + + Method (_AC4) { + If (LLessEqual (\FLVL, 4)) { + Return (CTOK (0)) + } Else { + Return (CTOK (0)) + } + } + + Name (_AL0, Package () { FAN0 }) + Name (_AL1, Package () { FAN1 }) + Name (_AL2, Package () { FAN2 }) + Name (_AL3, Package () { FAN3 }) + Name (_AL4, Package () { FAN4 }) + + PowerResource (FNP0, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 0)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (0, \FLVL) + Store (FAN0_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (1, \FLVL) + Store (FAN1_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP1, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 1)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (1, \FLVL) + Store (FAN1_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (2, \FLVL) + Store (FAN2_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP2, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 2)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (2, \FLVL) + Store (FAN2_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (3, \FLVL) + Store (FAN3_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP3, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 3)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (3, \FLVL) + Store (FAN3_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (4, \FLVL) + Store (FAN4_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP4, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 4)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (4, \FLVL) + Store (FAN4_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (4, \FLVL) + Store (FAN4_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + Device (FAN0) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 0) + Name (_PR0, Package () { FNP0 }) + } + + Device (FAN1) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 1) + Name (_PR0, Package () { FNP1 }) + } + + Device (FAN2) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 2) + Name (_PR0, Package () { FNP2 }) + } + + Device (FAN3) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 3) + Name (_PR0, Package () { FNP3 }) + } + + Device (FAN4) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 4) + Name (_PR0, Package () { FNP4 }) + } + } +} diff --git a/src/mainboard/google/jecht/variants/rikku/include/variant/gpio.h b/src/mainboard/google/jecht/variants/rikku/include/variant/gpio.h new file mode 100644 index 0000000000..f58ad24f67 --- /dev/null +++ b/src/mainboard/google/jecht/variants/rikku/include/variant/gpio.h @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef RIKKU_GPIO_H +#define RIKKU_GPIO_H + +#include <soc/gpio.h> + +static const struct gpio_config mainboard_gpio_config[] = { + PCH_GPIO_UNUSED, /* 0: UNUSED */ + PCH_GPIO_UNUSED, /* 1: UNUSED */ + PCH_GPIO_UNUSED, /* 2: UNUSED */ + PCH_GPIO_UNUSED, /* 3: UNUSED */ + PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ + PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ + PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ + PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ + PCH_GPIO_ACPI_SCI, /* 8: LAN_WAKE_L_Q */ + PCH_GPIO_OUT_HIGH, /* 9: PP3300_WLAN_EN */ + PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ + PCH_GPIO_UNUSED, /* 11: SMBALERT */ + PCH_GPIO_INPUT_INVERT, /* 12: RECOVERY_L */ + PCH_GPIO_UNUSED, /* 13: UNUSED */ + PCH_GPIO_UNUSED, /* 14: UNUSED */ + PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 16: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 17: PP3300_VP8_EN */ + PCH_GPIO_UNUSED, /* 18: UNUSED */ + PCH_GPIO_UNUSED, /* 19: UNUSED */ + PCH_GPIO_NATIVE, /* 20: NATIVE: CLK_PCIE_REQ2# */ + PCH_GPIO_NATIVE, /* 21: NATIVE: CLK_PCIE_REQ3# */ + PCH_GPIO_NATIVE, /* 22: NATIVE: CLK_PCIE_REQ4# */ + PCH_GPIO_UNUSED, /* 23: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 24: WLAN_OFF_L */ + PCH_GPIO_UNUSED, /* 25: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 26: USB_CTL_1 */ + PCH_GPIO_UNUSED, /* 27: UNUSED */ + PCH_GPIO_OUT_LOW, /* 28: USB_ILIM_SEL */ + PCH_GPIO_UNUSED, /* 29: UNUSED */ + PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSPWRACK_L */ + PCH_GPIO_NATIVE, /* 31: NATIVE: PCH_ACPRESENT */ + PCH_GPIO_NATIVE, /* 32: NATIVE: CLKRUN# */ + PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ + PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ + PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ + PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ + PCH_GPIO_UNUSED, /* 37: UNUSED */ + PCH_GPIO_UNUSED, /* 38: UNUSED */ + PCH_GPIO_UNUSED, /* 39: UNUSED */ + PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ + PCH_GPIO_NATIVE, /* 41: NATIVE: USB_OC1# */ + PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ + PCH_GPIO_NATIVE, /* 43: NATIVE: USB_OC3# */ + PCH_GPIO_UNUSED, /* 44: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 45: PP5000_CODEC_EN */ + PCH_GPIO_OUT_HIGH, /* 46: BT_DISABLE_L */ + PCH_GPIO_OUT_HIGH, /* 47: USB1_PWR_EN */ + PCH_GPIO_UNUSED, /* 48: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 49: POWER_LED */ + PCH_GPIO_OUT_HIGH, /* 50: VP8_DISABLE_L */ + PCH_GPIO_UNUSED, /* 51: UNUSED */ + PCH_GPIO_UNUSED, /* 52: UNUSED */ + PCH_GPIO_UNUSED, /* 53: UNUSED */ + PCH_GPIO_UNUSED, /* 54: UNUSED */ + PCH_GPIO_UNUSED, /* 55: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 56: USB2_PWR_EN */ + PCH_GPIO_OUT_HIGH, /* 57: USB3_PWR_EN */ + PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ + PCH_GPIO_OUT_HIGH, /* 59: PP3300_LAN_EN */ + PCH_GPIO_NATIVE, /* 60: NATIVE: SMB0ALERT# */ + PCH_GPIO_UNUSED, /* 61: UNUSED */ + PCH_GPIO_UNUSED, /* 62: UNUSED */ + PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ + PCH_GPIO_UNUSED, /* 64: UNUSED */ + PCH_GPIO_UNUSED, /* 65: UNUSED */ + PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 67: UNUSED */ + PCH_GPIO_UNUSED, /* 68: UNUSED */ + PCH_GPIO_UNUSED, /* 69: UNUSED */ + PCH_GPIO_UNUSED, /* 70: UNUSED */ + PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ + PCH_GPIO_UNUSED, /* 72: UNUSED */ + PCH_GPIO_UNUSED, /* 73: UNUSED */ + PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ + PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ + PCH_GPIO_UNUSED, /* 76: UNUSED */ + PCH_GPIO_UNUSED, /* 77: UNUSED */ + PCH_GPIO_UNUSED, /* 78: UNUSED */ + PCH_GPIO_UNUSED, /* 79: UNUSED */ + PCH_GPIO_UNUSED, /* 80: UNUSED */ + PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */ + PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ + PCH_GPIO_UNUSED, /* 83: UNUSED */ + PCH_GPIO_UNUSED, /* 84: UNUSED */ + PCH_GPIO_UNUSED, /* 85: UNUSED */ + PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 87: UNUSED */ + PCH_GPIO_UNUSED, /* 88: UNUSED */ + PCH_GPIO_UNUSED, /* 89: UNUSED */ + PCH_GPIO_UNUSED, /* 90: UNUSED */ + PCH_GPIO_UNUSED, /* 91: UNUSED */ + PCH_GPIO_UNUSED, /* 92: UNUSED */ + PCH_GPIO_UNUSED, /* 93: UNUSED */ + PCH_GPIO_UNUSED, /* 94: UNUSED */ + PCH_GPIO_END +}; + +#endif diff --git a/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h b/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h new file mode 100644 index 0000000000..b9144531e1 --- /dev/null +++ b/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef THERMAL_H +#define THERMAL_H + +#define TEMPERATURE_SENSOR_ID 0 /* PECI */ + +/* Fan is at default speed */ +#define FAN4_PWM 0x4d + +/* Fan is at LOW speed */ +#define FAN3_THRESHOLD_OFF 42 +#define FAN3_THRESHOLD_ON 47 +#define FAN3_PWM 0xa5 + +/* Fan is at MEDIUM speed */ +#define FAN2_THRESHOLD_OFF 54 +#define FAN2_THRESHOLD_ON 59 +#define FAN2_PWM 0xb2 + +/* Fan is at HIGH speed */ +#define FAN1_THRESHOLD_OFF 66 +#define FAN1_THRESHOLD_ON 71 +#define FAN1_PWM 0xc9 + +/* Fan is at FULL speed */ +#define FAN0_THRESHOLD_OFF 78 +#define FAN0_THRESHOLD_ON 83 +#define FAN0_PWM 0xd8 + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 95 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 105 + +#endif diff --git a/src/mainboard/google/jecht/variants/rikku/pei_data.c b/src/mainboard/google/jecht/variants/rikku/pei_data.c new file mode 100644 index 0000000000..4eeabbeec4 --- /dev/null +++ b/src/mainboard/google/jecht/variants/rikku/pei_data.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->ec_present = 0; + + /* P0: VP8 */ + pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0, + USB_PORT_MINI_PCIE); + /* P1: Port A, CN22 */ + pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, + USB_PORT_INTERNAL); + /* P2: Port B, CN23 */ + pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1, + USB_PORT_INTERNAL); + /* P3: WLAN */ + pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_MINI_PCIE); + /* P4: Port C, CN25 */ + pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, + USB_PORT_INTERNAL); + /* P5: Port D, CN25 */ + pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2, + USB_PORT_INTERNAL); + /* P6: Card Reader */ + pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_INTERNAL); + /* P7: EMPTY */ + pei_data_usb2_port(pei_data, 7, 0x0000, 0, 0, + USB_PORT_SKIP); + + /* P1: CN22 */ + pei_data_usb3_port(pei_data, 0, 1, 0, 0); + /* P2: CN23 */ + pei_data_usb3_port(pei_data, 1, 1, 1, 0); + /* P3: CN25 */ + pei_data_usb3_port(pei_data, 2, 1, 2, 0); + /* P4: CN25 */ + pei_data_usb3_port(pei_data, 3, 1, 2, 0); +} diff --git a/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl new file mode 100644 index 0000000000..78e7bf75c7 --- /dev/null +++ b/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl @@ -0,0 +1,447 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../thermal.h" + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 2 seconds + Name (_TSP, 20) + + Name (F0ON, FAN0_2_THRESHOLD_ON) + Name (F0OF, FAN0_2_THRESHOLD_OFF) + Name (F0PW, FAN0_2_PWM) + Name (F1ON, FAN1_2_THRESHOLD_ON) + Name (F1OF, FAN1_2_THRESHOLD_OFF) + Name (F1PW, FAN1_2_PWM) + Name (F2ON, FAN2_2_THRESHOLD_ON) + Name (F2OF, FAN2_2_THRESHOLD_OFF) + Name (F2PW, FAN2_2_PWM) + Name (F3ON, FAN3_2_THRESHOLD_ON) + Name (F3OF, FAN3_2_THRESHOLD_OFF) + Name (F3PW, FAN3_2_PWM) + Name (F4PW, FAN4_2_PWM) + Name (THTB, 2) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Thermal Table 0 + Method (TTB0, 0) { + Store (FAN0_0_THRESHOLD_ON, F0ON) + Store (FAN0_0_THRESHOLD_OFF, F0OF) + Store (FAN0_0_PWM, F0PW) + Store (FAN1_0_THRESHOLD_ON, F1ON) + Store (FAN1_0_THRESHOLD_OFF, F1OF) + Store (FAN1_0_PWM, F1PW) + Store (FAN2_0_THRESHOLD_ON, F2ON) + Store (FAN2_0_THRESHOLD_OFF, F2OF) + Store (FAN2_0_PWM, F2PW) + Store (FAN3_0_THRESHOLD_ON, F3ON) + Store (FAN3_0_THRESHOLD_OFF, F3OF) + Store (FAN3_0_PWM, F3PW) + Store (FAN4_0_PWM, F4PW) + Store (0, THTB) + } + + // Thermal Table 1 + Method (TTB1, 0) { + Store (FAN0_1_THRESHOLD_ON, F0ON) + Store (FAN0_1_THRESHOLD_OFF, F0OF) + Store (FAN0_1_PWM, F0PW) + Store (FAN1_1_THRESHOLD_ON, F1ON) + Store (FAN1_1_THRESHOLD_OFF, F1OF) + Store (FAN1_1_PWM, F1PW) + Store (FAN2_1_THRESHOLD_ON, F2ON) + Store (FAN2_1_THRESHOLD_OFF, F2OF) + Store (FAN2_1_PWM, F2PW) + Store (FAN3_1_THRESHOLD_ON, F3ON) + Store (FAN3_1_THRESHOLD_OFF, F3OF) + Store (FAN3_1_PWM, F3PW) + Store (FAN4_1_PWM, F4PW) + Store (1, THTB) + } + + // Thermal Table 2 + Method (TTB2, 0) { + Store (FAN0_2_THRESHOLD_ON, F0ON) + Store (FAN0_2_THRESHOLD_OFF, F0OF) + Store (FAN0_2_PWM, F0PW) + Store (FAN1_2_THRESHOLD_ON, F1ON) + Store (FAN1_2_THRESHOLD_OFF, F1OF) + Store (FAN1_2_PWM, F1PW) + Store (FAN2_2_THRESHOLD_ON, F2ON) + Store (FAN2_2_THRESHOLD_OFF, F2OF) + Store (FAN2_2_PWM, F2PW) + Store (FAN3_2_THRESHOLD_ON, F3ON) + Store (FAN3_2_THRESHOLD_OFF, F3OF) + Store (FAN3_2_PWM, F3PW) + Store (FAN4_2_PWM, F4PW) + Store (2, THTB) + } + + // Update Thermal Table + Method (UPTB, 0) { + // Get System Temperature via SuperIO TMPIN2 + Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN2, Local0) + + // Check for "no reading available + If (LEqual (Local0, 0x80)) { + Store (THERMAL_POLICY_0_THRESHOLD_ON, Local0) + } + + // Check for invalid readings + If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + Store (THERMAL_POLICY_0_THRESHOLD_ON, Local0) + } + + If (LEqual (THTB, 2)) { + If (LGreaterEqual (Local0, THERMAL_POLICY_0_THRESHOLD_ON)) { + TTB0 () + } ElseIf (LGreaterEqual (Local0, THERMAL_POLICY_1_THRESHOLD_ON)) { + TTB1 () + } + } ElseIf (LEqual (THTB, 1)) { + If (LGreaterEqual (Local0, THERMAL_POLICY_0_THRESHOLD_ON)) { + TTB0 () + } ElseIf (LLessEqual (Local0, THERMAL_POLICY_1_THRESHOLD_OFF)) { + TTB2 () + } + } Else { + If (LLess (Local0, THERMAL_POLICY_1_THRESHOLD_OFF)) { + TTB2 () + } ElseIf (LLessEqual (Local0, THERMAL_POLICY_0_THRESHOLD_OFF)) { + TTB1 () + } + } + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + // Start fan at state 4 = lowest temp state + Method (_INI) + { + Store (4, \FLVL) + Store (FAN4_2_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + + Method (TCHK, 0, Serialized) + { + // Update Thermal Table + UPTB () + + // Get CPU Temperature from PECI via SuperIO TMPIN3 + Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) + + // Check for "no reading available + If (LEqual (Local0, 0x80)) { + Return (CTOK (FAN0_0_THRESHOLD_ON)) + } + + // Check for invalid readings + If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + Return (CTOK (FAN0_0_THRESHOLD_ON)) + } + + // PECI raw value is an offset from Tj_max + Subtract (255, Local0, Local1) + + // Handle values greater than Tj_max + If (LGreaterEqual (Local1, \TMAX)) { + Return (CTOK (\TMAX)) + } + + // Subtract from Tj_max to get temperature + Subtract (\TMAX, Local1, Local0) + Return (CTOK (Local0)) + } + + Method (_TMP, 0, Serialized) + { + // Get temperature from SuperIO in deci-kelvin + Store (TCHK (), Local0) + + // Critical temperature in deci-kelvin + Store (CTOK (\TMAX), Local1) + + If (LGreaterEqual (Local0, Local1)) { + Store ("CRITICAL TEMPERATURE", Debug) + Store (Local0, Debug) + + // Wait 1 second for SuperIO to re-poll + Sleep (1000) + + // Re-read temperature from SuperIO + Store (TCHK (), Local0) + + Store ("RE-READ TEMPERATURE", Debug) + Store (Local0, Debug) + } + + Return (Local0) + } + + Method (_AC0) { + If (LLessEqual (\FLVL, 0)) { + Return (CTOK (F0OF)) + } Else { + Return (CTOK (F0ON)) + } + } + + Method (_AC1) { + If (LLessEqual (\FLVL, 1)) { + Return (CTOK (F1OF)) + } Else { + Return (CTOK (F1ON)) + } + } + + Method (_AC2) { + If (LLessEqual (\FLVL, 2)) { + Return (CTOK (F2OF)) + } Else { + Return (CTOK (F2ON)) + } + } + + Method (_AC3) { + If (LLessEqual (\FLVL, 3)) { + Return (CTOK (F3OF)) + } Else { + Return (CTOK (F3ON)) + } + } + + Method (_AC4) { + If (LLessEqual (\FLVL, 4)) { + Return (CTOK (0)) + } Else { + Return (CTOK (0)) + } + } + + Name (_AL0, Package () { FAN0 }) + Name (_AL1, Package () { FAN1 }) + Name (_AL2, Package () { FAN2 }) + Name (_AL3, Package () { FAN3 }) + Name (_AL4, Package () { FAN4 }) + + PowerResource (FNP0, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 0)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (0, \FLVL) + Store (F0PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (1, \FLVL) + Store (F1PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP1, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 1)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (1, \FLVL) + Store (F1PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (2, \FLVL) + Store (F2PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP2, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 2)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (2, \FLVL) + Store (F2PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (3, \FLVL) + Store (F3PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP3, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 3)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (3, \FLVL) + Store (F3PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (4, \FLVL) + Store (F4PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP4, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 4)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (4, \FLVL) + Store (F4PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (4, \FLVL) + Store (F4PW, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + Device (FAN0) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 0) + Name (_PR0, Package () { FNP0 }) + } + + Device (FAN1) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 1) + Name (_PR0, Package () { FNP1 }) + } + + Device (FAN2) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 2) + Name (_PR0, Package () { FNP2 }) + } + + Device (FAN3) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 3) + Name (_PR0, Package () { FNP3 }) + } + + Device (FAN4) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 4) + Name (_PR0, Package () { FNP4 }) + } + } +} diff --git a/src/mainboard/google/jecht/variants/tidus/include/variant/gpio.h b/src/mainboard/google/jecht/variants/tidus/include/variant/gpio.h new file mode 100644 index 0000000000..846fe816d4 --- /dev/null +++ b/src/mainboard/google/jecht/variants/tidus/include/variant/gpio.h @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef TIDUS_GPIO_H +#define TIDUS_GPIO_H + +#include <soc/gpio.h> + +static const struct gpio_config mainboard_gpio_config[] = { + PCH_GPIO_UNUSED, /* 0: UNUSED */ + PCH_GPIO_UNUSED, /* 1: UNUSED */ + PCH_GPIO_UNUSED, /* 2: UNUSED */ + PCH_GPIO_UNUSED, /* 3: UNUSED */ + PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ + PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ + PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ + PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ + PCH_GPIO_ACPI_SCI, /* 8: LAN_WAKE_L_Q */ + PCH_GPIO_OUT_HIGH, /* 9: PP3300_WLAN_EN */ + PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ + PCH_GPIO_UNUSED, /* 11: SMBALERT */ + PCH_GPIO_INPUT_INVERT, /* 12: RECOVERY_L */ + PCH_GPIO_UNUSED, /* 13: UNUSED */ + PCH_GPIO_UNUSED, /* 14: UNUSED */ + PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 16: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 17: PP3300_VP8_EN */ + PCH_GPIO_UNUSED, /* 18: UNUSED */ + PCH_GPIO_UNUSED, /* 19: UNUSED */ + PCH_GPIO_NATIVE, /* 20: NATIVE: CLK_PCIE_REQ2# */ + PCH_GPIO_NATIVE, /* 21: NATIVE: CLK_PCIE_REQ3# */ + PCH_GPIO_NATIVE, /* 22: NATIVE: CLK_PCIE_REQ4# */ + PCH_GPIO_UNUSED, /* 23: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 24: WLAN_OFF_L */ + PCH_GPIO_UNUSED, /* 25: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 26: USB_CTL_1 */ + PCH_GPIO_UNUSED, /* 27: UNUSED */ + PCH_GPIO_OUT_LOW, /* 28: USB_ILIM_SEL */ + PCH_GPIO_UNUSED, /* 29: UNUSED */ + PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSPWRACK_L */ + PCH_GPIO_NATIVE, /* 31: NATIVE: PCH_ACPRESENT */ + PCH_GPIO_NATIVE, /* 32: NATIVE: CLKRUN# */ + PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ + PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ + PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ + PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ + PCH_GPIO_UNUSED, /* 37: UNUSED */ + PCH_GPIO_UNUSED, /* 38: UNUSED */ + PCH_GPIO_UNUSED, /* 39: UNUSED */ + PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ + PCH_GPIO_NATIVE, /* 41: NATIVE: USB_OC1# */ + PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ + PCH_GPIO_NATIVE, /* 43: NATIVE: USB_OC3# */ + PCH_GPIO_UNUSED, /* 44: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 45: PP5000_CODEC_EN */ + PCH_GPIO_OUT_HIGH, /* 46: BT_DISABLE_L */ + PCH_GPIO_OUT_HIGH, /* 47: USB1_PWR_EN */ + PCH_GPIO_OUT_HIGH, /* 48: USB4_PWR_EN */ + PCH_GPIO_OUT_LOW, /* 49: POWER_LED */ + PCH_GPIO_OUT_HIGH, /* 50: VP8_DISABLE_L */ + PCH_GPIO_UNUSED, /* 51: UNUSED */ + PCH_GPIO_UNUSED, /* 52: UNUSED */ + PCH_GPIO_UNUSED, /* 53: UNUSED */ + PCH_GPIO_UNUSED, /* 54: UNUSED */ + PCH_GPIO_UNUSED, /* 55: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 56: USB2_PWR_EN */ + PCH_GPIO_OUT_HIGH, /* 57: USB3_PWR_EN */ + PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ + PCH_GPIO_OUT_HIGH, /* 59: PP3300_LAN_EN */ + PCH_GPIO_NATIVE, /* 60: NATIVE: SMB0ALERT# */ + PCH_GPIO_UNUSED, /* 61: UNUSED */ + PCH_GPIO_UNUSED, /* 62: UNUSED */ + PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ + PCH_GPIO_UNUSED, /* 64: UNUSED */ + PCH_GPIO_UNUSED, /* 65: UNUSED */ + PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 67: UNUSED */ + PCH_GPIO_UNUSED, /* 68: UNUSED */ + PCH_GPIO_UNUSED, /* 69: UNUSED */ + PCH_GPIO_UNUSED, /* 70: UNUSED */ + PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ + PCH_GPIO_UNUSED, /* 72: UNUSED */ + PCH_GPIO_UNUSED, /* 73: UNUSED */ + PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ + PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ + PCH_GPIO_UNUSED, /* 76: UNUSED */ + PCH_GPIO_UNUSED, /* 77: UNUSED */ + PCH_GPIO_UNUSED, /* 78: UNUSED */ + PCH_GPIO_UNUSED, /* 79: UNUSED */ + PCH_GPIO_UNUSED, /* 80: UNUSED */ + PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */ + PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ + PCH_GPIO_UNUSED, /* 83: UNUSED */ + PCH_GPIO_UNUSED, /* 84: UNUSED */ + PCH_GPIO_UNUSED, /* 85: UNUSED */ + PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 87: UNUSED */ + PCH_GPIO_UNUSED, /* 88: UNUSED */ + PCH_GPIO_UNUSED, /* 89: UNUSED */ + PCH_GPIO_UNUSED, /* 90: UNUSED */ + PCH_GPIO_UNUSED, /* 91: UNUSED */ + PCH_GPIO_UNUSED, /* 92: UNUSED */ + PCH_GPIO_UNUSED, /* 93: UNUSED */ + PCH_GPIO_UNUSED, /* 94: UNUSED */ + PCH_GPIO_END +}; + +#endif diff --git a/src/mainboard/google/jecht/variants/tidus/include/variant/thermal.h b/src/mainboard/google/jecht/variants/tidus/include/variant/thermal.h new file mode 100644 index 0000000000..4236424a35 --- /dev/null +++ b/src/mainboard/google/jecht/variants/tidus/include/variant/thermal.h @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef THERMAL_H +#define THERMAL_H + +#define TEMPERATURE_SENSOR_ID 0 /* PECI */ + +/* Thermal Policy 0 */ +/* Fan is at default speed */ +#define FAN4_0_PWM 0x4d + +/* Fan is at LOW speed */ +#define FAN3_0_THRESHOLD_OFF 62 +#define FAN3_0_THRESHOLD_ON 70 +#define FAN3_0_PWM 0x5e + +/* Fan is at MEDIUM speed */ +#define FAN2_0_THRESHOLD_OFF 68 +#define FAN2_0_THRESHOLD_ON 81 +#define FAN2_0_PWM 0x78 + +/* Fan is at HIGH speed */ +#define FAN1_0_THRESHOLD_OFF 78 +#define FAN1_0_THRESHOLD_ON 91 +#define FAN1_0_PWM 0x93 + +/* Fan is at FULL speed */ +#define FAN0_0_THRESHOLD_OFF 88 +#define FAN0_0_THRESHOLD_ON 100 +#define FAN0_0_PWM 0xb0 + +/* Thermal Policy 1 */ +/* Fan is at default speed */ +#define FAN4_1_PWM 0x4d + +/* Fan is at LOW speed */ +#define FAN3_1_THRESHOLD_OFF 62 +#define FAN3_1_THRESHOLD_ON 70 +#define FAN3_1_PWM 0x5e + +/* Fan is at MEDIUM speed */ +#define FAN2_1_THRESHOLD_OFF 68 +#define FAN2_1_THRESHOLD_ON 81 +#define FAN2_1_PWM 0x70 + +/* Fan is at HIGH speed */ +#define FAN1_1_THRESHOLD_OFF 78 +#define FAN1_1_THRESHOLD_ON 91 +#define FAN1_1_PWM 0x83 + +/* Fan is at FULL speed */ +#define FAN0_1_THRESHOLD_OFF 88 +#define FAN0_1_THRESHOLD_ON 100 +#define FAN0_1_PWM 0x93 + +/* Thermal Policy 2 */ +/* Fan is at default speed */ +#define FAN4_2_PWM 0x4d + +/* Fan is at LOW speed */ +#define FAN3_2_THRESHOLD_OFF 62 +#define FAN3_2_THRESHOLD_ON 70 +#define FAN3_2_PWM 0x59 + +/* Fan is at MEDIUM speed */ +#define FAN2_2_THRESHOLD_OFF 68 +#define FAN2_2_THRESHOLD_ON 81 +#define FAN2_2_PWM 0x63 + +/* Fan is at HIGH speed */ +#define FAN1_2_THRESHOLD_OFF 78 +#define FAN1_2_THRESHOLD_ON 91 +#define FAN1_2_PWM 0x6e + +/* Fan is at FULL speed */ +#define FAN0_2_THRESHOLD_OFF 88 +#define FAN0_2_THRESHOLD_ON 100 +#define FAN0_2_PWM 0x7e + +/* Threshold to change thermal policy */ +#define THERMAL_POLICY_0_THRESHOLD_OFF 38 +#define THERMAL_POLICY_0_THRESHOLD_ON 40 + +#define THERMAL_POLICY_1_THRESHOLD_OFF 33 +#define THERMAL_POLICY_1_THRESHOLD_ON 35 + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 103 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 105 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 105 + +#endif diff --git a/src/mainboard/google/jecht/variants/tidus/pei_data.c b/src/mainboard/google/jecht/variants/tidus/pei_data.c new file mode 100644 index 0000000000..7c03422553 --- /dev/null +++ b/src/mainboard/google/jecht/variants/tidus/pei_data.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->ec_present = 0; + + /* P0: VP8 */ + pei_data_usb2_port(pei_data, 0, 0x0064, 1, USB_OC_PIN_SKIP, + USB_PORT_MINI_PCIE); + /* P1: Port 3, USB3 */ + pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, + USB_PORT_INTERNAL); + /* P2: Port 4, USB4 */ + pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1, + USB_PORT_INTERNAL); + /* P3: Mini Card */ + pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_MINI_PCIE); + /* P4: Port 1, USB1 */ + pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, + USB_PORT_INTERNAL); + /* P5: Port 2, USB2 */ + pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2, + USB_PORT_INTERNAL); + /* P6: Card Reader */ + pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_INTERNAL); + /* P7: Pin Header */ + pei_data_usb2_port(pei_data, 7, 0x0040, 1, 3, + USB_PORT_INTERNAL); + + /* P1: USB1 */ + pei_data_usb3_port(pei_data, 0, 1, 2, 0); + /* P2: USB2 */ + pei_data_usb3_port(pei_data, 1, 1, 2, 0); + /* P3: USB3 */ + pei_data_usb3_port(pei_data, 2, 1, 0, 0); + /* P4: USB4 */ + pei_data_usb3_port(pei_data, 3, 1, 1, 0); +} |