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authorKyösti Mälkki <kyosti.malkki@gmail.com>2021-11-06 20:51:58 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2021-11-11 13:18:09 +0000
commit8355e6e72300d463cae243e1fa1bc4b665bf9fd8 (patch)
tree34948c22713bdabb288fb66bc1f6c8dc9f45a17c /src/mainboard/google/jecht
parent0cb116647e27b71f825e260b83a93a1bd1bfcf5e (diff)
google/beltino,jecht: Refactor ChromeOS GPIOs
Change-Id: I4052baca2d8041b2a6d6fd410fcf99248662d7a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/google/jecht')
-rw-r--r--src/mainboard/google/jecht/chromeos.c17
-rw-r--r--src/mainboard/google/jecht/onboard.h6
2 files changed, 18 insertions, 5 deletions
diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c
index ff4cef6a60..807e37fcb2 100644
--- a/src/mainboard/google/jecht/chromeos.c
+++ b/src/mainboard/google/jecht/chromeos.c
@@ -12,9 +12,6 @@
#include <southbridge/intel/lynxpoint/lp_gpio.h>
#include "onboard.h"
-#define GPIO_SPI_WP 58
-#define GPIO_REC_MODE 12
-
#define FLAG_SPI_WP 0
#define FLAG_REC_MODE 1
@@ -30,6 +27,16 @@ void fill_lb_gpios(struct lb_gpios *gpios)
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
+static bool raw_write_protect_state(void)
+{
+ return get_gpio(GPIO_SPI_WP);
+}
+
+static bool raw_recovery_mode_switch(void)
+{
+ return !get_gpio(GPIO_REC_MODE);
+}
+
int get_write_protect_state(void)
{
const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
@@ -48,11 +55,11 @@ void init_bootmode_straps(void)
const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */
- if (get_gpio(GPIO_SPI_WP))
+ if (raw_write_protect_state())
flags |= (1 << FLAG_SPI_WP);
/* Recovery: GPIO12 = RECOVERY_L, active low */
- if (!get_gpio(GPIO_REC_MODE))
+ if (raw_recovery_mode_switch())
flags |= (1 << FLAG_REC_MODE);
/* Developer: Virtual */
diff --git a/src/mainboard/google/jecht/onboard.h b/src/mainboard/google/jecht/onboard.h
index 1c37d7228d..a6ba80a7b3 100644
--- a/src/mainboard/google/jecht/onboard.h
+++ b/src/mainboard/google/jecht/onboard.h
@@ -37,4 +37,10 @@ enum {
#define IT8772F_GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO)
#define IT8772F_SUPERIO_DEV PNP_DEV(IT8772F_BASE, 0)
+/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */
+#define GPIO_SPI_WP 58
+
+/* Recovery: GPIO12 = RECOVERY_L, active low */
+#define GPIO_REC_MODE 12
+
#endif