Combine Broadwell Chromeboxes using variant board scheme

Combine existing boards google/guado, rikku, and tidus using
their common reference board google/jecht as a base.

Additional changes besides simple consolidation include:
 - simplify power LED functions
 - simplify HDA verb definitions using azelia macros
 - use common SoC functions to generate FADT table
 - correct FADT table header version
 - remove unused haswell_pci_irqs.asl
 - remove unused header includes (various)
 - set sane default fan speed (0x4d) for all variants

Variant setup modeled after google/beltino

Change-Id: I77a2dffe9601734916a33fd04ead98016ad0bc4b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17913
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

16 files changed, 2448 insertions, 0 deletions

diff --git a/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl
new file mode 100644
index 0000000000..1cd1b9b713
--- /dev/null
+++ b/src/mainboard/google/jecht/variants/guado/include/variant/acpi/thermal.asl
@@ -0,0 +1,339 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "../thermal.h"
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+	ThermalZone (THRM)
+	{
+		Name (_TC1, 0x02)
+		Name (_TC2, 0x05)
+
+		// Thermal zone polling frequency: 10 seconds
+		Name (_TZP, 100)
+
+		// Thermal sampling period for passive cooling: 2 seconds
+		Name (_TSP, 20)
+
+		// Convert from Degrees C to 1/10 Kelvin for ACPI
+		Method (CTOK, 1) {
+			// 10th of Degrees C
+			Multiply (Arg0, 10, Local0)
+
+			// Convert to Kelvin
+			Add (Local0, 2732, Local0)
+
+			Return (Local0)
+		}
+
+		// Threshold for OS to shutdown
+		Method (_CRT, 0, Serialized)
+		{
+			Return (CTOK (\TCRT))
+		}
+
+		// Threshold for passive cooling
+		Method (_PSV, 0, Serialized)
+		{
+			Return (CTOK (\TPSV))
+		}
+
+		// Processors used for passive cooling
+		Method (_PSL, 0, Serialized)
+		{
+			Return (\PPKG ())
+		}
+
+		// Start fan at state 4 = lowest temp state
+		Method (_INI)
+		{
+			Store (4, \FLVL)
+			Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+			Notify (\_TZ.THRM, 0x81)
+		}
+
+		Method (TCHK, 0, Serialized)
+		{
+			// Get CPU Temperature from PECI via SuperIO TMPIN3
+			Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0)
+
+			// Check for "no reading available
+			If (LEqual (Local0, 0x80)) {
+				Return (CTOK (FAN0_THRESHOLD_ON))
+			}
+
+			// Check for invalid readings
+			If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) {
+				Return (CTOK (FAN0_THRESHOLD_ON))
+			}
+
+			// PECI raw value is an offset from Tj_max
+			Subtract (255, Local0, Local1)
+
+			// Handle values greater than Tj_max
+			If (LGreaterEqual (Local1, \TMAX)) {
+				Return (CTOK (\TMAX))
+			}
+
+			// Subtract from Tj_max to get temperature
+			Subtract (\TMAX, Local1, Local0)
+			Return (CTOK (Local0))
+		}
+
+		Method (_TMP, 0, Serialized)
+		{
+			// Get temperature from SuperIO in deci-kelvin
+			Store (TCHK (), Local0)
+
+			// Critical temperature in deci-kelvin
+			Store (CTOK (\TMAX), Local1)
+
+			If (LGreaterEqual (Local0, Local1)) {
+				Store ("CRITICAL TEMPERATURE", Debug)
+				Store (Local0, Debug)
+
+				// Wait 1 second for SuperIO to re-poll
+				Sleep (1000)
+
+				// Re-read temperature from SuperIO
+				Store (TCHK (), Local0)
+
+				Store ("RE-READ TEMPERATURE", Debug)
+				Store (Local0, Debug)
+			}
+
+			Return (Local0)
+		}
+
+		Method (_AC0) {
+			If (LLessEqual (\FLVL, 0)) {
+				Return (CTOK (FAN0_THRESHOLD_OFF))
+			} Else {
+				Return (CTOK (FAN0_THRESHOLD_ON))
+			}
+		}
+
+		Method (_AC1) {
+			If (LLessEqual (\FLVL, 1)) {
+				Return (CTOK (FAN1_THRESHOLD_OFF))
+			} Else {
+				Return (CTOK (FAN1_THRESHOLD_ON))
+			}
+		}
+
+		Method (_AC2) {
+			If (LLessEqual (\FLVL, 2)) {
+				Return (CTOK (FAN2_THRESHOLD_OFF))
+			} Else {
+				Return (CTOK (FAN2_THRESHOLD_ON))
+			}
+		}
+
+		Method (_AC3) {
+			If (LLessEqual (\FLVL, 3)) {
+				Return (CTOK (FAN3_THRESHOLD_OFF))
+			} Else {
+				Return (CTOK (FAN3_THRESHOLD_ON))
+			}
+		}
+
+		Method (_AC4) {
+			If (LLessEqual (\FLVL, 4)) {
+				Return (CTOK (0))
+			} Else {
+				Return (CTOK (0))
+			}
+		}
+
+		Name (_AL0, Package () { FAN0 })
+		Name (_AL1, Package () { FAN1 })
+		Name (_AL2, Package () { FAN2 })
+		Name (_AL3, Package () { FAN3 })
+		Name (_AL4, Package () { FAN4 })
+
+		PowerResource (FNP0, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 0)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				If (LNot (_STA ())) {
+					Store (0, \FLVL)
+					Store (FAN0_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+			Method (_OFF) {
+				If (_STA ()) {
+					Store (1, \FLVL)
+					Store (FAN1_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+		}
+
+		PowerResource (FNP1, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 1)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				If (LNot (_STA ())) {
+					Store (1, \FLVL)
+					Store (FAN1_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+			Method (_OFF) {
+				If (_STA ()) {
+					Store (2, \FLVL)
+					Store (FAN2_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+		}
+
+		PowerResource (FNP2, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 2)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				If (LNot (_STA ())) {
+					Store (2, \FLVL)
+					Store (FAN2_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+			Method (_OFF) {
+				If (_STA ()) {
+					Store (3, \FLVL)
+					Store (FAN3_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+		}
+
+		PowerResource (FNP3, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 3)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				If (LNot (_STA ())) {
+					Store (3, \FLVL)
+					Store (FAN3_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+			Method (_OFF) {
+				If (_STA ()) {
+					Store (4, \FLVL)
+					Store (FAN4_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+		}
+
+		PowerResource (FNP4, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 4)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				If (LNot (_STA ())) {
+					Store (4, \FLVL)
+					Store (FAN4_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+			Method (_OFF) {
+				If (_STA ()) {
+					Store (4, \FLVL)
+					Store (FAN4_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+		}
+
+		Device (FAN0)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 0)
+			Name (_PR0, Package () { FNP0 })
+		}
+
+		Device (FAN1)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 1)
+			Name (_PR0, Package () { FNP1 })
+		}
+
+		Device (FAN2)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 2)
+			Name (_PR0, Package () { FNP2 })
+		}
+
+		Device (FAN3)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 3)
+			Name (_PR0, Package () { FNP3 })
+		}
+
+		Device (FAN4)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 4)
+			Name (_PR0, Package () { FNP4 })
+		}
+	}
+}
diff --git a/src/mainboard/google/jecht/variants/guado/include/variant/gpio.h b/src/mainboard/google/jecht/variants/guado/include/variant/gpio.h
new file mode 100644
index 0000000000..4c167e3a58
--- /dev/null
+++ b/src/mainboard/google/jecht/variants/guado/include/variant/gpio.h
@@ -0,0 +1,120 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef GUADO_GPIO_H
+#define GUADO_GPIO_H
+
+#include <soc/gpio.h>
+
+static const struct gpio_config mainboard_gpio_config[] = {
+	PCH_GPIO_UNUSED,        /* 0: UNUSED */
+	PCH_GPIO_UNUSED,        /* 1: UNUSED */
+	PCH_GPIO_UNUSED,        /* 2: UNUSED */
+	PCH_GPIO_UNUSED,        /* 3: UNUSED */
+	PCH_GPIO_NATIVE,        /* 4: NATIVE: I2C0_SDA_GPIO4 */
+	PCH_GPIO_NATIVE,        /* 5: NATIVE: I2C0_SCL_GPIO5 */
+	PCH_GPIO_NATIVE,        /* 6: NATIVE: I2C1_SDA_GPIO6 */
+	PCH_GPIO_NATIVE,        /* 7: NATIVE: I2C1_SCL_GPIO7 */
+	PCH_GPIO_ACPI_SCI,      /* 8: LAN_WAKE_L_Q */
+	PCH_GPIO_OUT_HIGH,      /* 9: PP3300_WLAN_EN */
+	PCH_GPIO_ACPI_SCI,      /* 10: WLAN_WAKE_L_Q */
+	PCH_GPIO_UNUSED,        /* 11: SMBALERT */
+	PCH_GPIO_INPUT_INVERT,  /* 12: RECOVERY_L */
+	PCH_GPIO_UNUSED,        /* 13: UNUSED */
+	PCH_GPIO_UNUSED,        /* 14: UNUSED */
+	PCH_GPIO_UNUSED,        /* 15: UNUSED (STRAP) */
+	PCH_GPIO_UNUSED,        /* 16: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 17: PP3300_VP8_EN */
+	PCH_GPIO_UNUSED,        /* 18: UNUSED */
+	PCH_GPIO_UNUSED,        /* 19: UNUSED */
+	PCH_GPIO_NATIVE,        /* 20: NATIVE: CLK_PCIE_REQ2# */
+	PCH_GPIO_NATIVE,        /* 21: NATIVE: CLK_PCIE_REQ3# */
+	PCH_GPIO_NATIVE,        /* 22: NATIVE: CLK_PCIE_REQ4# */
+	PCH_GPIO_UNUSED,        /* 23: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 24: WLAN_OFF_L */
+	PCH_GPIO_UNUSED,        /* 25: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 26: USB_CTL_1 */
+	PCH_GPIO_UNUSED,        /* 27: UNUSED */
+	PCH_GPIO_OUT_LOW,      /* 28: USB_ILIM_SEL */
+	PCH_GPIO_UNUSED,        /* 29: UNUSED */
+	PCH_GPIO_NATIVE,        /* 30: NATIVE: PCH_SUSPWRACK_L */
+	PCH_GPIO_NATIVE,        /* 31: NATIVE: PCH_ACPRESENT */
+	PCH_GPIO_NATIVE,        /* 32: NATIVE: CLKRUN# */
+	PCH_GPIO_NATIVE,        /* 33: NATIVE: DEVSLP0 */
+	PCH_GPIO_ACPI_SMI,      /* 34: EC_SMI_L */
+	PCH_GPIO_ACPI_SMI,      /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
+	PCH_GPIO_ACPI_SCI,      /* 36: EC_SCI_L */
+	PCH_GPIO_UNUSED,        /* 37: UNUSED */
+	PCH_GPIO_UNUSED,        /* 38: UNUSED */
+	PCH_GPIO_UNUSED,        /* 39: UNUSED */
+	PCH_GPIO_NATIVE,        /* 40: NATIVE: USB_OC0# */
+	PCH_GPIO_NATIVE,        /* 41: NATIVE: USB_OC1# */
+	PCH_GPIO_NATIVE,        /* 42: NATIVE: USB_OC2# */
+	PCH_GPIO_NATIVE,        /* 43: NATIVE: USB_OC3# */
+	PCH_GPIO_UNUSED,        /* 44: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 45: PP5000_CODEC_EN */
+	PCH_GPIO_OUT_HIGH,      /* 46: BT_DISABLE_L */
+	PCH_GPIO_OUT_HIGH,      /* 47: USB1_PWR_EN */
+	PCH_GPIO_UNUSED,        /* 48: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 49: POWER_LED */
+	PCH_GPIO_OUT_HIGH,      /* 50: VP8_DISABLE_L */
+	PCH_GPIO_UNUSED,        /* 51: UNUSED */
+	PCH_GPIO_UNUSED,        /* 52: UNUSED */
+	PCH_GPIO_UNUSED,        /* 53: UNUSED */
+	PCH_GPIO_UNUSED,        /* 54: UNUSED */
+	PCH_GPIO_UNUSED,        /* 55: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 56: USB2_PWR_EN */
+	PCH_GPIO_OUT_HIGH,      /* 57: USB3_PWR_EN */
+	PCH_GPIO_INPUT,         /* 58: PCH_SPI_WP_D */
+	PCH_GPIO_OUT_HIGH,      /* 59: PP3300_LAN_EN */
+	PCH_GPIO_NATIVE,        /* 60: NATIVE: SMB0ALERT# */
+	PCH_GPIO_UNUSED,        /* 61: UNUSED */
+	PCH_GPIO_UNUSED,        /* 62: UNUSED */
+	PCH_GPIO_NATIVE,        /* 63: NATIVE: PCH_SLP_S5_L */
+	PCH_GPIO_UNUSED,        /* 64: UNUSED */
+	PCH_GPIO_UNUSED,        /* 65: UNUSED */
+	PCH_GPIO_UNUSED,        /* 66: UNUSED (STRAP) */
+	PCH_GPIO_UNUSED,        /* 67: UNUSED */
+	PCH_GPIO_UNUSED,        /* 68: UNUSED */
+	PCH_GPIO_UNUSED,        /* 69: UNUSED */
+	PCH_GPIO_UNUSED,        /* 70: UNUSED */
+	PCH_GPIO_NATIVE,        /* 71: NATIVE: MODPHY_EN */
+	PCH_GPIO_UNUSED,        /* 72: UNUSED */
+	PCH_GPIO_UNUSED,        /* 73: UNUSED */
+	PCH_GPIO_NATIVE,        /* 74: NATIVE: SMB_ME1_DAT */
+	PCH_GPIO_NATIVE,        /* 75: NATIVE: SMB_ME1_CLK */
+	PCH_GPIO_UNUSED,        /* 76: UNUSED */
+	PCH_GPIO_UNUSED,        /* 77: UNUSED */
+	PCH_GPIO_UNUSED,        /* 78: UNUSED */
+	PCH_GPIO_UNUSED,        /* 79: UNUSED */
+	PCH_GPIO_UNUSED,        /* 80: UNUSED */
+	PCH_GPIO_NATIVE,        /* 81: NATIVE: SPKR */
+	PCH_GPIO_NATIVE,        /* 82: NATIVE: EC_RCIN_L */
+	PCH_GPIO_UNUSED,        /* 83: UNUSED */
+	PCH_GPIO_UNUSED,        /* 84: UNUSED */
+	PCH_GPIO_UNUSED,        /* 85: UNUSED */
+	PCH_GPIO_UNUSED,        /* 86: UNUSED (STRAP) */
+	PCH_GPIO_UNUSED,        /* 87: UNUSED */
+	PCH_GPIO_UNUSED,        /* 88: UNUSED */
+	PCH_GPIO_UNUSED,        /* 89: UNUSED */
+	PCH_GPIO_UNUSED,        /* 90: UNUSED */
+	PCH_GPIO_UNUSED,        /* 91: UNUSED */
+	PCH_GPIO_UNUSED,        /* 92: UNUSED */
+	PCH_GPIO_UNUSED,        /* 93: UNUSED */
+	PCH_GPIO_UNUSED,        /* 94: UNUSED */
+	PCH_GPIO_END
+};
+
+#endif
diff --git a/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h b/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h
new file mode 100644
index 0000000000..d299b14d08
--- /dev/null
+++ b/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef THERMAL_H
+#define THERMAL_H
+
+#define TEMPERATURE_SENSOR_ID		0	/* PECI */
+
+/* Fan is at default speed */
+#define FAN4_PWM		0x4d
+
+/* Fan is at LOW speed */
+#define FAN3_THRESHOLD_OFF	40
+#define FAN3_THRESHOLD_ON	50
+#define FAN3_PWM		0x55
+
+/* Fan is at MEDIUM speed */
+#define FAN2_THRESHOLD_OFF	55
+#define FAN2_THRESHOLD_ON	67
+#define FAN2_PWM		0xa6
+
+/* Fan is at HIGH speed */
+#define FAN1_THRESHOLD_OFF	65
+#define FAN1_THRESHOLD_ON	70
+#define FAN1_PWM		0xc0
+
+/* Fan is at FULL speed */
+#define FAN0_THRESHOLD_OFF	90
+#define FAN0_THRESHOLD_ON	100
+#define FAN0_PWM		0xff
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE	104
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE	95
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE		105
+
+#endif
diff --git a/src/mainboard/google/jecht/variants/guado/pei_data.c b/src/mainboard/google/jecht/variants/guado/pei_data.c
new file mode 100644
index 0000000000..1b5ea51532
--- /dev/null
+++ b/src/mainboard/google/jecht/variants/guado/pei_data.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+	pei_data->ec_present = 0;
+
+	/* P0: VP8 */
+	pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0,
+			   USB_PORT_MINI_PCIE);
+	/* P1: Port A, CN22 */
+	pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0,
+			   USB_PORT_INTERNAL);
+	/* P2: Port B, CN23 */
+	pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1,
+			   USB_PORT_INTERNAL);
+	/* P3: WLAN */
+	pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_MINI_PCIE);
+	/* P4: Port C, CN25 */
+	pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2,
+			   USB_PORT_INTERNAL);
+	/* P5: Port D, CN25 */
+	pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2,
+			   USB_PORT_INTERNAL);
+	/* P6: Card Reader */
+	pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_INTERNAL);
+	/* P7: EMPTY */
+	pei_data_usb2_port(pei_data, 7, 0x0000, 0, 0,
+			   USB_PORT_SKIP);
+
+	/* P1: CN22 */
+	pei_data_usb3_port(pei_data, 0, 1, 0, 0);
+	/* P2: CN23 */
+	pei_data_usb3_port(pei_data, 1, 1, 1, 0);
+	/* P3: CN25 */
+	pei_data_usb3_port(pei_data, 2, 1, 2, 0);
+	/* P4: CN25 */
+	pei_data_usb3_port(pei_data, 3, 1, 2, 0);
+}
diff --git a/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl
new file mode 100644
index 0000000000..1cd1b9b713
--- /dev/null
+++ b/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/thermal.asl
@@ -0,0 +1,339 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "../thermal.h"
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+	ThermalZone (THRM)
+	{
+		Name (_TC1, 0x02)
+		Name (_TC2, 0x05)
+
+		// Thermal zone polling frequency: 10 seconds
+		Name (_TZP, 100)
+
+		// Thermal sampling period for passive cooling: 2 seconds
+		Name (_TSP, 20)
+
+		// Convert from Degrees C to 1/10 Kelvin for ACPI
+		Method (CTOK, 1) {
+			// 10th of Degrees C
+			Multiply (Arg0, 10, Local0)
+
+			// Convert to Kelvin
+			Add (Local0, 2732, Local0)
+
+			Return (Local0)
+		}
+
+		// Threshold for OS to shutdown
+		Method (_CRT, 0, Serialized)
+		{
+			Return (CTOK (\TCRT))
+		}
+
+		// Threshold for passive cooling
+		Method (_PSV, 0, Serialized)
+		{
+			Return (CTOK (\TPSV))
+		}
+
+		// Processors used for passive cooling
+		Method (_PSL, 0, Serialized)
+		{
+			Return (\PPKG ())
+		}
+
+		// Start fan at state 4 = lowest temp state
+		Method (_INI)
+		{
+			Store (4, \FLVL)
+			Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+			Notify (\_TZ.THRM, 0x81)
+		}
+
+		Method (TCHK, 0, Serialized)
+		{
+			// Get CPU Temperature from PECI via SuperIO TMPIN3
+			Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0)
+
+			// Check for "no reading available
+			If (LEqual (Local0, 0x80)) {
+				Return (CTOK (FAN0_THRESHOLD_ON))
+			}
+
+			// Check for invalid readings
+			If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) {
+				Return (CTOK (FAN0_THRESHOLD_ON))
+			}
+
+			// PECI raw value is an offset from Tj_max
+			Subtract (255, Local0, Local1)
+
+			// Handle values greater than Tj_max
+			If (LGreaterEqual (Local1, \TMAX)) {
+				Return (CTOK (\TMAX))
+			}
+
+			// Subtract from Tj_max to get temperature
+			Subtract (\TMAX, Local1, Local0)
+			Return (CTOK (Local0))
+		}
+
+		Method (_TMP, 0, Serialized)
+		{
+			// Get temperature from SuperIO in deci-kelvin
+			Store (TCHK (), Local0)
+
+			// Critical temperature in deci-kelvin
+			Store (CTOK (\TMAX), Local1)
+
+			If (LGreaterEqual (Local0, Local1)) {
+				Store ("CRITICAL TEMPERATURE", Debug)
+				Store (Local0, Debug)
+
+				// Wait 1 second for SuperIO to re-poll
+				Sleep (1000)
+
+				// Re-read temperature from SuperIO
+				Store (TCHK (), Local0)
+
+				Store ("RE-READ TEMPERATURE", Debug)
+				Store (Local0, Debug)
+			}
+
+			Return (Local0)
+		}
+
+		Method (_AC0) {
+			If (LLessEqual (\FLVL, 0)) {
+				Return (CTOK (FAN0_THRESHOLD_OFF))
+			} Else {
+				Return (CTOK (FAN0_THRESHOLD_ON))
+			}
+		}
+
+		Method (_AC1) {
+			If (LLessEqual (\FLVL, 1)) {
+				Return (CTOK (FAN1_THRESHOLD_OFF))
+			} Else {
+				Return (CTOK (FAN1_THRESHOLD_ON))
+			}
+		}
+
+		Method (_AC2) {
+			If (LLessEqual (\FLVL, 2)) {
+				Return (CTOK (FAN2_THRESHOLD_OFF))
+			} Else {
+				Return (CTOK (FAN2_THRESHOLD_ON))
+			}
+		}
+
+		Method (_AC3) {
+			If (LLessEqual (\FLVL, 3)) {
+				Return (CTOK (FAN3_THRESHOLD_OFF))
+			} Else {
+				Return (CTOK (FAN3_THRESHOLD_ON))
+			}
+		}
+
+		Method (_AC4) {
+			If (LLessEqual (\FLVL, 4)) {
+				Return (CTOK (0))
+			} Else {
+				Return (CTOK (0))
+			}
+		}
+
+		Name (_AL0, Package () { FAN0 })
+		Name (_AL1, Package () { FAN1 })
+		Name (_AL2, Package () { FAN2 })
+		Name (_AL3, Package () { FAN3 })
+		Name (_AL4, Package () { FAN4 })
+
+		PowerResource (FNP0, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 0)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				If (LNot (_STA ())) {
+					Store (0, \FLVL)
+					Store (FAN0_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+			Method (_OFF) {
+				If (_STA ()) {
+					Store (1, \FLVL)
+					Store (FAN1_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+		}
+
+		PowerResource (FNP1, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 1)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				If (LNot (_STA ())) {
+					Store (1, \FLVL)
+					Store (FAN1_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+			Method (_OFF) {
+				If (_STA ()) {
+					Store (2, \FLVL)
+					Store (FAN2_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+		}
+
+		PowerResource (FNP2, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 2)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				If (LNot (_STA ())) {
+					Store (2, \FLVL)
+					Store (FAN2_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+			Method (_OFF) {
+				If (_STA ()) {
+					Store (3, \FLVL)
+					Store (FAN3_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+		}
+
+		PowerResource (FNP3, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 3)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				If (LNot (_STA ())) {
+					Store (3, \FLVL)
+					Store (FAN3_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+			Method (_OFF) {
+				If (_STA ()) {
+					Store (4, \FLVL)
+					Store (FAN4_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+		}
+
+		PowerResource (FNP4, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 4)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				If (LNot (_STA ())) {
+					Store (4, \FLVL)
+					Store (FAN4_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+			Method (_OFF) {
+				If (_STA ()) {
+					Store (4, \FLVL)
+					Store (FAN4_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+		}
+
+		Device (FAN0)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 0)
+			Name (_PR0, Package () { FNP0 })
+		}
+
+		Device (FAN1)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 1)
+			Name (_PR0, Package () { FNP1 })
+		}
+
+		Device (FAN2)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 2)
+			Name (_PR0, Package () { FNP2 })
+		}
+
+		Device (FAN3)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 3)
+			Name (_PR0, Package () { FNP3 })
+		}
+
+		Device (FAN4)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 4)
+			Name (_PR0, Package () { FNP4 })
+		}
+	}
+}
diff --git a/src/mainboard/google/jecht/variants/jecht/include/variant/gpio.h b/src/mainboard/google/jecht/variants/jecht/include/variant/gpio.h
new file mode 100644
index 0000000000..94e6516ce7
--- /dev/null
+++ b/src/mainboard/google/jecht/variants/jecht/include/variant/gpio.h
@@ -0,0 +1,120 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef JECHT_GPIO_H
+#define JECHT_GPIO_H
+
+#include <soc/gpio.h>
+
+static const struct gpio_config mainboard_gpio_config[] = {
+	PCH_GPIO_UNUSED,        /* 0: UNUSED */
+	PCH_GPIO_UNUSED,        /* 1: UNUSED */
+	PCH_GPIO_UNUSED,        /* 2: UNUSED */
+	PCH_GPIO_UNUSED,        /* 3: UNUSED */
+	PCH_GPIO_NATIVE,        /* 4: NATIVE: I2C0_SDA_GPIO4 */
+	PCH_GPIO_NATIVE,        /* 5: NATIVE: I2C0_SCL_GPIO5 */
+	PCH_GPIO_NATIVE,        /* 6: NATIVE: I2C1_SDA_GPIO6 */
+	PCH_GPIO_NATIVE,        /* 7: NATIVE: I2C1_SCL_GPIO7 */
+	PCH_GPIO_ACPI_SCI,      /* 8: LAN_WAKE_L_Q */
+	PCH_GPIO_OUT_HIGH,      /* 9: PP3300_WLAN_EN */
+	PCH_GPIO_ACPI_SCI,      /* 10: WLAN_WAKE_L_Q */
+	PCH_GPIO_UNUSED,        /* 11: SMBALERT */
+	PCH_GPIO_INPUT_INVERT,  /* 12: RECOVERY_L */
+	PCH_GPIO_UNUSED,        /* 13: UNUSED */
+	PCH_GPIO_UNUSED,        /* 14: UNUSED */
+	PCH_GPIO_UNUSED,        /* 15: UNUSED (STRAP) */
+	PCH_GPIO_UNUSED,        /* 16: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 17: PP3300_VP8_EN */
+	PCH_GPIO_UNUSED,        /* 18: UNUSED */
+	PCH_GPIO_UNUSED,        /* 19: UNUSED */
+	PCH_GPIO_NATIVE,        /* 20: NATIVE: CLK_PCIE_REQ2# */
+	PCH_GPIO_NATIVE,        /* 21: NATIVE: CLK_PCIE_REQ3# */
+	PCH_GPIO_NATIVE,        /* 22: NATIVE: CLK_PCIE_REQ4# */
+	PCH_GPIO_UNUSED,        /* 23: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 24: WLAN_OFF_L */
+	PCH_GPIO_UNUSED,        /* 25: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 26: USB_CTL_1 */
+	PCH_GPIO_UNUSED,        /* 27: UNUSED */
+	PCH_GPIO_OUT_LOW,      /* 28: USB_ILIM_SEL */
+	PCH_GPIO_UNUSED,        /* 29: UNUSED */
+	PCH_GPIO_NATIVE,        /* 30: NATIVE: PCH_SUSPWRACK_L */
+	PCH_GPIO_NATIVE,        /* 31: NATIVE: PCH_ACPRESENT */
+	PCH_GPIO_NATIVE,        /* 32: NATIVE: CLKRUN# */
+	PCH_GPIO_NATIVE,        /* 33: NATIVE: DEVSLP0 */
+	PCH_GPIO_ACPI_SMI,      /* 34: EC_SMI_L */
+	PCH_GPIO_ACPI_SMI,      /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
+	PCH_GPIO_ACPI_SCI,      /* 36: EC_SCI_L */
+	PCH_GPIO_UNUSED,        /* 37: UNUSED */
+	PCH_GPIO_UNUSED,        /* 38: UNUSED */
+	PCH_GPIO_UNUSED,        /* 39: UNUSED */
+	PCH_GPIO_NATIVE,        /* 40: NATIVE: USB_OC0# */
+	PCH_GPIO_NATIVE,        /* 41: NATIVE: USB_OC1# */
+	PCH_GPIO_NATIVE,        /* 42: NATIVE: USB_OC2# */
+	PCH_GPIO_NATIVE,        /* 43: NATIVE: USB_OC3# */
+	PCH_GPIO_UNUSED,        /* 44: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 45: PP5000_CODEC_EN */
+	PCH_GPIO_OUT_HIGH,      /* 46: BT_DISABLE_L */
+	PCH_GPIO_OUT_HIGH,      /* 47: USB1_PWR_EN */
+	PCH_GPIO_UNUSED,        /* 48: UNUSED */
+	PCH_GPIO_UNUSED,        /* 49: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 50: VP8_DISABLE_L */
+	PCH_GPIO_UNUSED,        /* 51: UNUSED */
+	PCH_GPIO_UNUSED,        /* 52: UNUSED */
+	PCH_GPIO_UNUSED,        /* 53: UNUSED */
+	PCH_GPIO_UNUSED,        /* 54: UNUSED */
+	PCH_GPIO_UNUSED,        /* 55: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 56: USB2_PWR_EN */
+	PCH_GPIO_OUT_HIGH,      /* 57: USB3_PWR_EN */
+	PCH_GPIO_INPUT,         /* 58: PCH_SPI_WP_D */
+	PCH_GPIO_OUT_HIGH,      /* 59: PP3300_LAN_EN */
+	PCH_GPIO_NATIVE,        /* 60: NATIVE: SMB0ALERT# */
+	PCH_GPIO_UNUSED,        /* 61: UNUSED */
+	PCH_GPIO_UNUSED,        /* 62: UNUSED */
+	PCH_GPIO_NATIVE,        /* 63: NATIVE: PCH_SLP_S5_L */
+	PCH_GPIO_UNUSED,        /* 64: UNUSED */
+	PCH_GPIO_UNUSED,        /* 65: UNUSED */
+	PCH_GPIO_UNUSED,        /* 66: UNUSED (STRAP) */
+	PCH_GPIO_UNUSED,        /* 67: UNUSED */
+	PCH_GPIO_UNUSED,        /* 68: UNUSED */
+	PCH_GPIO_UNUSED,        /* 69: UNUSED */
+	PCH_GPIO_UNUSED,        /* 70: UNUSED */
+	PCH_GPIO_NATIVE,        /* 71: NATIVE: MODPHY_EN */
+	PCH_GPIO_UNUSED,        /* 72: UNUSED */
+	PCH_GPIO_UNUSED,        /* 73: UNUSED */
+	PCH_GPIO_NATIVE,        /* 74: NATIVE: SMB_ME1_DAT */
+	PCH_GPIO_NATIVE,        /* 75: NATIVE: SMB_ME1_CLK */
+	PCH_GPIO_UNUSED,        /* 76: UNUSED */
+	PCH_GPIO_UNUSED,        /* 77: UNUSED */
+	PCH_GPIO_UNUSED,        /* 78: UNUSED */
+	PCH_GPIO_UNUSED,        /* 79: UNUSED */
+	PCH_GPIO_UNUSED,        /* 80: UNUSED */
+	PCH_GPIO_NATIVE,        /* 81: NATIVE: SPKR */
+	PCH_GPIO_NATIVE,        /* 82: NATIVE: EC_RCIN_L */
+	PCH_GPIO_UNUSED,        /* 83: UNUSED */
+	PCH_GPIO_UNUSED,        /* 84: UNUSED */
+	PCH_GPIO_UNUSED,        /* 85: UNUSED */
+	PCH_GPIO_UNUSED,        /* 86: UNUSED (STRAP) */
+	PCH_GPIO_UNUSED,        /* 87: UNUSED */
+	PCH_GPIO_UNUSED,        /* 88: UNUSED */
+	PCH_GPIO_UNUSED,        /* 89: UNUSED */
+	PCH_GPIO_UNUSED,        /* 90: UNUSED */
+	PCH_GPIO_UNUSED,        /* 91: UNUSED */
+	PCH_GPIO_UNUSED,        /* 92: UNUSED */
+	PCH_GPIO_UNUSED,        /* 93: UNUSED */
+	PCH_GPIO_UNUSED,        /* 94: UNUSED */
+	PCH_GPIO_END
+};
+
+#endif
diff --git a/src/mainboard/google/jecht/variants/jecht/include/variant/thermal.h b/src/mainboard/google/jecht/variants/jecht/include/variant/thermal.h
new file mode 100644
index 0000000000..29559eb754
--- /dev/null
+++ b/src/mainboard/google/jecht/variants/jecht/include/variant/thermal.h
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef THERMAL_H
+#define THERMAL_H
+
+#define TEMPERATURE_SENSOR_ID		0	/* PECI */
+
+/* Fan is at default speed */
+#define FAN4_PWM		0x4d
+
+/* Fan is at LOW speed */
+#define FAN3_THRESHOLD_OFF      50
+#define FAN3_THRESHOLD_ON       55
+#define FAN3_PWM                0x76
+
+/* Fan is at MEDIUM speed */
+#define FAN2_THRESHOLD_OFF      59
+#define FAN2_THRESHOLD_ON       65
+#define FAN2_PWM                0x98
+
+/* Fan is at HIGH speed */
+#define FAN1_THRESHOLD_OFF      68
+#define FAN1_THRESHOLD_ON       75
+#define FAN1_PWM                0xbf
+
+/* Fan is at FULL speed */
+#define FAN0_THRESHOLD_OFF      80
+#define FAN0_THRESHOLD_ON       86
+#define FAN0_PWM                0xdc
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE		98
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE		95
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE			105
+
+#endif
diff --git a/src/mainboard/google/jecht/variants/jecht/pei_data.c b/src/mainboard/google/jecht/variants/jecht/pei_data.c
new file mode 100644
index 0000000000..1b5ea51532
--- /dev/null
+++ b/src/mainboard/google/jecht/variants/jecht/pei_data.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+	pei_data->ec_present = 0;
+
+	/* P0: VP8 */
+	pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0,
+			   USB_PORT_MINI_PCIE);
+	/* P1: Port A, CN22 */
+	pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0,
+			   USB_PORT_INTERNAL);
+	/* P2: Port B, CN23 */
+	pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1,
+			   USB_PORT_INTERNAL);
+	/* P3: WLAN */
+	pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_MINI_PCIE);
+	/* P4: Port C, CN25 */
+	pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2,
+			   USB_PORT_INTERNAL);
+	/* P5: Port D, CN25 */
+	pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2,
+			   USB_PORT_INTERNAL);
+	/* P6: Card Reader */
+	pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_INTERNAL);
+	/* P7: EMPTY */
+	pei_data_usb2_port(pei_data, 7, 0x0000, 0, 0,
+			   USB_PORT_SKIP);
+
+	/* P1: CN22 */
+	pei_data_usb3_port(pei_data, 0, 1, 0, 0);
+	/* P2: CN23 */
+	pei_data_usb3_port(pei_data, 1, 1, 1, 0);
+	/* P3: CN25 */
+	pei_data_usb3_port(pei_data, 2, 1, 2, 0);
+	/* P4: CN25 */
+	pei_data_usb3_port(pei_data, 3, 1, 2, 0);
+}
diff --git a/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl
new file mode 100644
index 0000000000..151ac51289
--- /dev/null
+++ b/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/thermal.asl
@@ -0,0 +1,339 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "../thermal.h"
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+	ThermalZone (THRM)
+	{
+		Name (_TC1, 0x02)
+		Name (_TC2, 0x05)
+
+		// Thermal zone polling frequency: 10 seconds
+		Name (_TZP, 100)
+
+		// Thermal sampling period for passive cooling: 2 seconds
+		Name (_TSP, 20)
+
+		// Convert from Degrees C to 1/10 Kelvin for ACPI
+		Method (CTOK, 1) {
+			// 10th of Degrees C
+			Multiply (Arg0, 10, Local0)
+
+			// Convert to Kelvin
+			Add (Local0, 2732, Local0)
+
+			Return (Local0)
+		}
+
+		// Threshold for OS to shutdown
+		Method (_CRT, 0, Serialized)
+		{
+			Return (CTOK (\TCRT))
+		}
+
+		// Threshold for passive cooling
+		Method (_PSV, 0, Serialized)
+		{
+			Return (CTOK (\TPSV))
+		}
+
+		// Processors used for passive cooling
+		Method (_PSL, 0, Serialized)
+		{
+			Return (\PPKG ())
+		}
+
+		// Start fan at state 4 = lowest temp state
+		Method (_INI)
+		{
+			Store (4, \FLVL)
+			Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+			Notify (\_TZ.THRM, 0x81)
+		}
+
+		Method (TCHK, 0, Serialized)
+		{
+			// Get CPU Temperature from PECI via SuperIO TMPIN3
+			Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0)
+
+			// Check for "no reading available
+			If (LEqual (Local0, 0x80)) {
+				Return (CTOK (FAN0_THRESHOLD_ON))
+			}
+
+			// Check for invalid readings
+			If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) {
+				Return (CTOK (FAN0_THRESHOLD_ON))
+			}
+
+			// PECI raw value is an offset from Tj_max
+			Subtract (255, Local0, Local1)
+
+			// Handle values greater than Tj_max
+			If (LGreaterEqual (Local1, \TMAX)) {
+				Return (CTOK (\TMAX))
+			}
+
+			// Subtract from Tj_max to get temperature
+			Subtract (\TMAX, Local1, Local0)
+			Return (CTOK (Local0))
+		}
+
+		Method (_TMP, 0, Serialized)
+		{
+			// Get temperature from SuperIO in deci-kelvin
+			Store (TCHK (), Local0)
+
+			// Critical temperature in deci-kelvin
+			Store (CTOK (\TMAX), Local1)
+
+			If (LGreaterEqual (Local0, Local1)) {
+				Store ("CRITICAL TEMPERATURE", Debug)
+				Store (Local0, Debug)
+
+				// Wait 1 second for SuperIO to re-poll
+				Sleep (1000)
+
+				// Re-read temperature from SuperIO
+				Store (TCHK (), Local0)
+
+				Store ("RE-READ TEMPERATURE", Debug)
+				Store (Local0, Debug)
+			}
+
+			Return (Local0)
+		}
+
+		Method (_AC0) {
+			If (LLessEqual (\FLVL, 0)) {
+				Return (CTOK (FAN0_THRESHOLD_OFF))
+			} Else {
+				Return (CTOK (FAN0_THRESHOLD_ON))
+			}
+		}
+
+		Method (_AC1) {
+			If (LLessEqual (\FLVL, 1)) {
+				Return (CTOK (FAN1_THRESHOLD_OFF))
+			} Else {
+				Return (CTOK (FAN1_THRESHOLD_ON))
+			}
+		}
+
+		Method (_AC2) {
+			If (LLessEqual (\FLVL, 2)) {
+				Return (CTOK (FAN2_THRESHOLD_OFF))
+			} Else {
+				Return (CTOK (FAN2_THRESHOLD_ON))
+			}
+		}
+
+		Method (_AC3) {
+			If (LLessEqual (\FLVL, 3)) {
+				Return (CTOK (FAN3_THRESHOLD_OFF))
+			} Else {
+				Return (CTOK (FAN3_THRESHOLD_ON))
+			}
+		}
+
+		Method (_AC4) {
+			If (LLessEqual (\FLVL, 4)) {
+				Return (CTOK (0))
+			} Else {
+				Return (CTOK (0))
+			}
+		}
+
+		Name (_AL0, Package () { FAN0 })
+		Name (_AL1, Package () { FAN1 })
+		Name (_AL2, Package () { FAN2 })
+		Name (_AL3, Package () { FAN3 })
+		Name (_AL4, Package () { FAN4 })
+
+		PowerResource (FNP0, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 0)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				If (LNot (_STA ())) {
+					Store (0, \FLVL)
+					Store (FAN0_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+			Method (_OFF) {
+				If (_STA ()) {
+					Store (1, \FLVL)
+					Store (FAN1_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+		}
+
+		PowerResource (FNP1, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 1)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				If (LNot (_STA ())) {
+					Store (1, \FLVL)
+					Store (FAN1_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+			Method (_OFF) {
+				If (_STA ()) {
+					Store (2, \FLVL)
+					Store (FAN2_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+		}
+
+		PowerResource (FNP2, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 2)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				If (LNot (_STA ())) {
+					Store (2, \FLVL)
+					Store (FAN2_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+			Method (_OFF) {
+				If (_STA ()) {
+					Store (3, \FLVL)
+					Store (FAN3_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+		}
+
+		PowerResource (FNP3, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 3)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				If (LNot (_STA ())) {
+					Store (3, \FLVL)
+					Store (FAN3_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+			Method (_OFF) {
+				If (_STA ()) {
+					Store (4, \FLVL)
+					Store (FAN4_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+		}
+
+		PowerResource (FNP4, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 4)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				If (LNot (_STA ())) {
+					Store (4, \FLVL)
+					Store (FAN4_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+			Method (_OFF) {
+				If (_STA ()) {
+					Store (4, \FLVL)
+					Store (FAN4_PWM,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+		}
+
+		Device (FAN0)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 0)
+			Name (_PR0, Package () { FNP0 })
+		}
+
+		Device (FAN1)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 1)
+			Name (_PR0, Package () { FNP1 })
+		}
+
+		Device (FAN2)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 2)
+			Name (_PR0, Package () { FNP2 })
+		}
+
+		Device (FAN3)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 3)
+			Name (_PR0, Package () { FNP3 })
+		}
+
+		Device (FAN4)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 4)
+			Name (_PR0, Package () { FNP4 })
+		}
+	}
+}
diff --git a/src/mainboard/google/jecht/variants/rikku/include/variant/gpio.h b/src/mainboard/google/jecht/variants/rikku/include/variant/gpio.h
new file mode 100644
index 0000000000..f58ad24f67
--- /dev/null
+++ b/src/mainboard/google/jecht/variants/rikku/include/variant/gpio.h
@@ -0,0 +1,120 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef RIKKU_GPIO_H
+#define RIKKU_GPIO_H
+
+#include <soc/gpio.h>
+
+static const struct gpio_config mainboard_gpio_config[] = {
+	PCH_GPIO_UNUSED,        /* 0: UNUSED */
+	PCH_GPIO_UNUSED,        /* 1: UNUSED */
+	PCH_GPIO_UNUSED,        /* 2: UNUSED */
+	PCH_GPIO_UNUSED,        /* 3: UNUSED */
+	PCH_GPIO_NATIVE,        /* 4: NATIVE: I2C0_SDA_GPIO4 */
+	PCH_GPIO_NATIVE,        /* 5: NATIVE: I2C0_SCL_GPIO5 */
+	PCH_GPIO_NATIVE,        /* 6: NATIVE: I2C1_SDA_GPIO6 */
+	PCH_GPIO_NATIVE,        /* 7: NATIVE: I2C1_SCL_GPIO7 */
+	PCH_GPIO_ACPI_SCI,      /* 8: LAN_WAKE_L_Q */
+	PCH_GPIO_OUT_HIGH,      /* 9: PP3300_WLAN_EN */
+	PCH_GPIO_ACPI_SCI,      /* 10: WLAN_WAKE_L_Q */
+	PCH_GPIO_UNUSED,        /* 11: SMBALERT */
+	PCH_GPIO_INPUT_INVERT,  /* 12: RECOVERY_L */
+	PCH_GPIO_UNUSED,        /* 13: UNUSED */
+	PCH_GPIO_UNUSED,        /* 14: UNUSED */
+	PCH_GPIO_UNUSED,        /* 15: UNUSED (STRAP) */
+	PCH_GPIO_UNUSED,        /* 16: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 17: PP3300_VP8_EN */
+	PCH_GPIO_UNUSED,        /* 18: UNUSED */
+	PCH_GPIO_UNUSED,        /* 19: UNUSED */
+	PCH_GPIO_NATIVE,        /* 20: NATIVE: CLK_PCIE_REQ2# */
+	PCH_GPIO_NATIVE,        /* 21: NATIVE: CLK_PCIE_REQ3# */
+	PCH_GPIO_NATIVE,        /* 22: NATIVE: CLK_PCIE_REQ4# */
+	PCH_GPIO_UNUSED,        /* 23: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 24: WLAN_OFF_L */
+	PCH_GPIO_UNUSED,        /* 25: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 26: USB_CTL_1 */
+	PCH_GPIO_UNUSED,        /* 27: UNUSED */
+	PCH_GPIO_OUT_LOW,      /* 28: USB_ILIM_SEL */
+	PCH_GPIO_UNUSED,        /* 29: UNUSED */
+	PCH_GPIO_NATIVE,        /* 30: NATIVE: PCH_SUSPWRACK_L */
+	PCH_GPIO_NATIVE,        /* 31: NATIVE: PCH_ACPRESENT */
+	PCH_GPIO_NATIVE,        /* 32: NATIVE: CLKRUN# */
+	PCH_GPIO_NATIVE,        /* 33: NATIVE: DEVSLP0 */
+	PCH_GPIO_ACPI_SMI,      /* 34: EC_SMI_L */
+	PCH_GPIO_ACPI_SMI,      /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
+	PCH_GPIO_ACPI_SCI,      /* 36: EC_SCI_L */
+	PCH_GPIO_UNUSED,        /* 37: UNUSED */
+	PCH_GPIO_UNUSED,        /* 38: UNUSED */
+	PCH_GPIO_UNUSED,        /* 39: UNUSED */
+	PCH_GPIO_NATIVE,        /* 40: NATIVE: USB_OC0# */
+	PCH_GPIO_NATIVE,        /* 41: NATIVE: USB_OC1# */
+	PCH_GPIO_NATIVE,        /* 42: NATIVE: USB_OC2# */
+	PCH_GPIO_NATIVE,        /* 43: NATIVE: USB_OC3# */
+	PCH_GPIO_UNUSED,        /* 44: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 45: PP5000_CODEC_EN */
+	PCH_GPIO_OUT_HIGH,      /* 46: BT_DISABLE_L */
+	PCH_GPIO_OUT_HIGH,      /* 47: USB1_PWR_EN */
+	PCH_GPIO_UNUSED,        /* 48: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 49: POWER_LED */
+	PCH_GPIO_OUT_HIGH,      /* 50: VP8_DISABLE_L */
+	PCH_GPIO_UNUSED,        /* 51: UNUSED */
+	PCH_GPIO_UNUSED,        /* 52: UNUSED */
+	PCH_GPIO_UNUSED,        /* 53: UNUSED */
+	PCH_GPIO_UNUSED,        /* 54: UNUSED */
+	PCH_GPIO_UNUSED,        /* 55: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 56: USB2_PWR_EN */
+	PCH_GPIO_OUT_HIGH,      /* 57: USB3_PWR_EN */
+	PCH_GPIO_INPUT,         /* 58: PCH_SPI_WP_D */
+	PCH_GPIO_OUT_HIGH,      /* 59: PP3300_LAN_EN */
+	PCH_GPIO_NATIVE,        /* 60: NATIVE: SMB0ALERT# */
+	PCH_GPIO_UNUSED,        /* 61: UNUSED */
+	PCH_GPIO_UNUSED,        /* 62: UNUSED */
+	PCH_GPIO_NATIVE,        /* 63: NATIVE: PCH_SLP_S5_L */
+	PCH_GPIO_UNUSED,        /* 64: UNUSED */
+	PCH_GPIO_UNUSED,        /* 65: UNUSED */
+	PCH_GPIO_UNUSED,        /* 66: UNUSED (STRAP) */
+	PCH_GPIO_UNUSED,        /* 67: UNUSED */
+	PCH_GPIO_UNUSED,        /* 68: UNUSED */
+	PCH_GPIO_UNUSED,        /* 69: UNUSED */
+	PCH_GPIO_UNUSED,        /* 70: UNUSED */
+	PCH_GPIO_NATIVE,        /* 71: NATIVE: MODPHY_EN */
+	PCH_GPIO_UNUSED,        /* 72: UNUSED */
+	PCH_GPIO_UNUSED,        /* 73: UNUSED */
+	PCH_GPIO_NATIVE,        /* 74: NATIVE: SMB_ME1_DAT */
+	PCH_GPIO_NATIVE,        /* 75: NATIVE: SMB_ME1_CLK */
+	PCH_GPIO_UNUSED,        /* 76: UNUSED */
+	PCH_GPIO_UNUSED,        /* 77: UNUSED */
+	PCH_GPIO_UNUSED,        /* 78: UNUSED */
+	PCH_GPIO_UNUSED,        /* 79: UNUSED */
+	PCH_GPIO_UNUSED,        /* 80: UNUSED */
+	PCH_GPIO_NATIVE,        /* 81: NATIVE: SPKR */
+	PCH_GPIO_NATIVE,        /* 82: NATIVE: EC_RCIN_L */
+	PCH_GPIO_UNUSED,        /* 83: UNUSED */
+	PCH_GPIO_UNUSED,        /* 84: UNUSED */
+	PCH_GPIO_UNUSED,        /* 85: UNUSED */
+	PCH_GPIO_UNUSED,        /* 86: UNUSED (STRAP) */
+	PCH_GPIO_UNUSED,        /* 87: UNUSED */
+	PCH_GPIO_UNUSED,        /* 88: UNUSED */
+	PCH_GPIO_UNUSED,        /* 89: UNUSED */
+	PCH_GPIO_UNUSED,        /* 90: UNUSED */
+	PCH_GPIO_UNUSED,        /* 91: UNUSED */
+	PCH_GPIO_UNUSED,        /* 92: UNUSED */
+	PCH_GPIO_UNUSED,        /* 93: UNUSED */
+	PCH_GPIO_UNUSED,        /* 94: UNUSED */
+	PCH_GPIO_END
+};
+
+#endif
diff --git a/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h b/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h
new file mode 100644
index 0000000000..b9144531e1
--- /dev/null
+++ b/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef THERMAL_H
+#define THERMAL_H
+
+#define TEMPERATURE_SENSOR_ID		0	/* PECI */
+
+/* Fan is at default speed */
+#define FAN4_PWM		0x4d
+
+/* Fan is at LOW speed */
+#define FAN3_THRESHOLD_OFF	42
+#define FAN3_THRESHOLD_ON	47
+#define FAN3_PWM		0xa5
+
+/* Fan is at MEDIUM speed */
+#define FAN2_THRESHOLD_OFF	54
+#define FAN2_THRESHOLD_ON	59
+#define FAN2_PWM		0xb2
+
+/* Fan is at HIGH speed */
+#define FAN1_THRESHOLD_OFF	66
+#define FAN1_THRESHOLD_ON	71
+#define FAN1_PWM		0xc9
+
+/* Fan is at FULL speed */
+#define FAN0_THRESHOLD_OFF	78
+#define FAN0_THRESHOLD_ON	83
+#define FAN0_PWM		0xd8
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE	100
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE	95
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE		105
+
+#endif
diff --git a/src/mainboard/google/jecht/variants/rikku/pei_data.c b/src/mainboard/google/jecht/variants/rikku/pei_data.c
new file mode 100644
index 0000000000..4eeabbeec4
--- /dev/null
+++ b/src/mainboard/google/jecht/variants/rikku/pei_data.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+	pei_data->ec_present = 0;
+
+	/* P0: VP8 */
+	pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0,
+			   USB_PORT_MINI_PCIE);
+	/* P1: Port A, CN22 */
+	pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0,
+			   USB_PORT_INTERNAL);
+	/* P2: Port B, CN23 */
+	pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1,
+			   USB_PORT_INTERNAL);
+	/* P3: WLAN */
+	pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_MINI_PCIE);
+	/* P4: Port C, CN25 */
+	pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2,
+			   USB_PORT_INTERNAL);
+	/* P5: Port D, CN25 */
+	pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2,
+			   USB_PORT_INTERNAL);
+	/* P6: Card Reader */
+	pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_INTERNAL);
+	/* P7: EMPTY */
+	pei_data_usb2_port(pei_data, 7, 0x0000, 0, 0,
+			   USB_PORT_SKIP);
+
+	/* P1: CN22 */
+	pei_data_usb3_port(pei_data, 0, 1, 0, 0);
+	/* P2: CN23 */
+	pei_data_usb3_port(pei_data, 1, 1, 1, 0);
+	/* P3: CN25 */
+	pei_data_usb3_port(pei_data, 2, 1, 2, 0);
+	/* P4: CN25 */
+	pei_data_usb3_port(pei_data, 3, 1, 2, 0);
+}
diff --git a/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl b/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl
new file mode 100644
index 0000000000..78e7bf75c7
--- /dev/null
+++ b/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/thermal.asl
@@ -0,0 +1,447 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "../thermal.h"
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+	ThermalZone (THRM)
+	{
+		Name (_TC1, 0x02)
+		Name (_TC2, 0x05)
+
+		// Thermal zone polling frequency: 10 seconds
+		Name (_TZP, 100)
+
+		// Thermal sampling period for passive cooling: 2 seconds
+		Name (_TSP, 20)
+
+		Name (F0ON, FAN0_2_THRESHOLD_ON)
+		Name (F0OF, FAN0_2_THRESHOLD_OFF)
+		Name (F0PW, FAN0_2_PWM)
+		Name (F1ON, FAN1_2_THRESHOLD_ON)
+		Name (F1OF, FAN1_2_THRESHOLD_OFF)
+		Name (F1PW, FAN1_2_PWM)
+		Name (F2ON, FAN2_2_THRESHOLD_ON)
+		Name (F2OF, FAN2_2_THRESHOLD_OFF)
+		Name (F2PW, FAN2_2_PWM)
+		Name (F3ON, FAN3_2_THRESHOLD_ON)
+		Name (F3OF, FAN3_2_THRESHOLD_OFF)
+		Name (F3PW, FAN3_2_PWM)
+		Name (F4PW, FAN4_2_PWM)
+		Name (THTB, 2)
+
+		// Convert from Degrees C to 1/10 Kelvin for ACPI
+		Method (CTOK, 1) {
+			// 10th of Degrees C
+			Multiply (Arg0, 10, Local0)
+
+			// Convert to Kelvin
+			Add (Local0, 2732, Local0)
+
+			Return (Local0)
+		}
+
+		// Thermal Table 0
+		Method (TTB0, 0) {
+			Store (FAN0_0_THRESHOLD_ON, F0ON)
+			Store (FAN0_0_THRESHOLD_OFF, F0OF)
+			Store (FAN0_0_PWM, F0PW)
+			Store (FAN1_0_THRESHOLD_ON, F1ON)
+			Store (FAN1_0_THRESHOLD_OFF, F1OF)
+			Store (FAN1_0_PWM, F1PW)
+			Store (FAN2_0_THRESHOLD_ON, F2ON)
+			Store (FAN2_0_THRESHOLD_OFF, F2OF)
+			Store (FAN2_0_PWM, F2PW)
+			Store (FAN3_0_THRESHOLD_ON, F3ON)
+			Store (FAN3_0_THRESHOLD_OFF, F3OF)
+			Store (FAN3_0_PWM, F3PW)
+			Store (FAN4_0_PWM, F4PW)
+			Store (0, THTB)
+		}
+
+		// Thermal Table 1
+		Method (TTB1, 0) {
+			Store (FAN0_1_THRESHOLD_ON, F0ON)
+			Store (FAN0_1_THRESHOLD_OFF, F0OF)
+			Store (FAN0_1_PWM, F0PW)
+			Store (FAN1_1_THRESHOLD_ON, F1ON)
+			Store (FAN1_1_THRESHOLD_OFF, F1OF)
+			Store (FAN1_1_PWM, F1PW)
+			Store (FAN2_1_THRESHOLD_ON, F2ON)
+			Store (FAN2_1_THRESHOLD_OFF, F2OF)
+			Store (FAN2_1_PWM, F2PW)
+			Store (FAN3_1_THRESHOLD_ON, F3ON)
+			Store (FAN3_1_THRESHOLD_OFF, F3OF)
+			Store (FAN3_1_PWM, F3PW)
+			Store (FAN4_1_PWM, F4PW)
+			Store (1, THTB)
+		}
+
+		// Thermal Table 2
+		Method (TTB2, 0) {
+			Store (FAN0_2_THRESHOLD_ON, F0ON)
+			Store (FAN0_2_THRESHOLD_OFF, F0OF)
+			Store (FAN0_2_PWM, F0PW)
+			Store (FAN1_2_THRESHOLD_ON, F1ON)
+			Store (FAN1_2_THRESHOLD_OFF, F1OF)
+			Store (FAN1_2_PWM, F1PW)
+			Store (FAN2_2_THRESHOLD_ON, F2ON)
+			Store (FAN2_2_THRESHOLD_OFF, F2OF)
+			Store (FAN2_2_PWM, F2PW)
+			Store (FAN3_2_THRESHOLD_ON, F3ON)
+			Store (FAN3_2_THRESHOLD_OFF, F3OF)
+			Store (FAN3_2_PWM, F3PW)
+			Store (FAN4_2_PWM, F4PW)
+			Store (2, THTB)
+		}
+
+		// Update Thermal Table
+		Method (UPTB, 0) {
+			// Get System Temperature via SuperIO TMPIN2
+			Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN2, Local0)
+
+			// Check for "no reading available
+			If (LEqual (Local0, 0x80)) {
+				Store (THERMAL_POLICY_0_THRESHOLD_ON, Local0)
+			}
+
+			// Check for invalid readings
+			If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) {
+				Store (THERMAL_POLICY_0_THRESHOLD_ON, Local0)
+			}
+
+			If (LEqual (THTB, 2)) {
+				If (LGreaterEqual (Local0, THERMAL_POLICY_0_THRESHOLD_ON)) {
+					TTB0 ()
+				} ElseIf (LGreaterEqual (Local0, THERMAL_POLICY_1_THRESHOLD_ON)) {
+					TTB1 ()
+				}
+			} ElseIf (LEqual (THTB, 1)) {
+				If (LGreaterEqual (Local0, THERMAL_POLICY_0_THRESHOLD_ON)) {
+					TTB0 ()
+				} ElseIf (LLessEqual (Local0, THERMAL_POLICY_1_THRESHOLD_OFF)) {
+					TTB2 ()
+				}
+			} Else {
+				If (LLess (Local0, THERMAL_POLICY_1_THRESHOLD_OFF)) {
+					TTB2 ()
+				} ElseIf (LLessEqual (Local0, THERMAL_POLICY_0_THRESHOLD_OFF)) {
+					TTB1 ()
+				}
+			}
+		}
+
+		// Threshold for OS to shutdown
+		Method (_CRT, 0, Serialized)
+		{
+			Return (CTOK (\TCRT))
+		}
+
+		// Threshold for passive cooling
+		Method (_PSV, 0, Serialized)
+		{
+			Return (CTOK (\TPSV))
+		}
+
+		// Processors used for passive cooling
+		Method (_PSL, 0, Serialized)
+		{
+			Return (\PPKG ())
+		}
+
+		// Start fan at state 4 = lowest temp state
+		Method (_INI)
+		{
+			Store (4, \FLVL)
+			Store (FAN4_2_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+			Notify (\_TZ.THRM, 0x81)
+		}
+
+		Method (TCHK, 0, Serialized)
+		{
+			// Update Thermal Table
+			UPTB ()
+
+			// Get CPU Temperature from PECI via SuperIO TMPIN3
+			Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0)
+
+			// Check for "no reading available
+			If (LEqual (Local0, 0x80)) {
+				Return (CTOK (FAN0_0_THRESHOLD_ON))
+			}
+
+			// Check for invalid readings
+			If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) {
+				Return (CTOK (FAN0_0_THRESHOLD_ON))
+			}
+
+			// PECI raw value is an offset from Tj_max
+			Subtract (255, Local0, Local1)
+
+			// Handle values greater than Tj_max
+			If (LGreaterEqual (Local1, \TMAX)) {
+				Return (CTOK (\TMAX))
+			}
+
+			// Subtract from Tj_max to get temperature
+			Subtract (\TMAX, Local1, Local0)
+			Return (CTOK (Local0))
+		}
+
+		Method (_TMP, 0, Serialized)
+		{
+			// Get temperature from SuperIO in deci-kelvin
+			Store (TCHK (), Local0)
+
+			// Critical temperature in deci-kelvin
+			Store (CTOK (\TMAX), Local1)
+
+			If (LGreaterEqual (Local0, Local1)) {
+				Store ("CRITICAL TEMPERATURE", Debug)
+				Store (Local0, Debug)
+
+				// Wait 1 second for SuperIO to re-poll
+				Sleep (1000)
+
+				// Re-read temperature from SuperIO
+				Store (TCHK (), Local0)
+
+				Store ("RE-READ TEMPERATURE", Debug)
+				Store (Local0, Debug)
+			}
+
+			Return (Local0)
+		}
+
+		Method (_AC0) {
+			If (LLessEqual (\FLVL, 0)) {
+				Return (CTOK (F0OF))
+			} Else {
+				Return (CTOK (F0ON))
+			}
+		}
+
+		Method (_AC1) {
+			If (LLessEqual (\FLVL, 1)) {
+				Return (CTOK (F1OF))
+			} Else {
+				Return (CTOK (F1ON))
+			}
+		}
+
+		Method (_AC2) {
+			If (LLessEqual (\FLVL, 2)) {
+				Return (CTOK (F2OF))
+			} Else {
+				Return (CTOK (F2ON))
+			}
+		}
+
+		Method (_AC3) {
+			If (LLessEqual (\FLVL, 3)) {
+				Return (CTOK (F3OF))
+			} Else {
+				Return (CTOK (F3ON))
+			}
+		}
+
+		Method (_AC4) {
+			If (LLessEqual (\FLVL, 4)) {
+				Return (CTOK (0))
+			} Else {
+				Return (CTOK (0))
+			}
+		}
+
+		Name (_AL0, Package () { FAN0 })
+		Name (_AL1, Package () { FAN1 })
+		Name (_AL2, Package () { FAN2 })
+		Name (_AL3, Package () { FAN3 })
+		Name (_AL4, Package () { FAN4 })
+
+		PowerResource (FNP0, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 0)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				If (LNot (_STA ())) {
+					Store (0, \FLVL)
+					Store (F0PW,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+			Method (_OFF) {
+				If (_STA ()) {
+					Store (1, \FLVL)
+					Store (F1PW,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+		}
+
+		PowerResource (FNP1, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 1)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				If (LNot (_STA ())) {
+					Store (1, \FLVL)
+					Store (F1PW,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+			Method (_OFF) {
+				If (_STA ()) {
+					Store (2, \FLVL)
+					Store (F2PW,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+		}
+
+		PowerResource (FNP2, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 2)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				If (LNot (_STA ())) {
+					Store (2, \FLVL)
+					Store (F2PW,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+			Method (_OFF) {
+				If (_STA ()) {
+					Store (3, \FLVL)
+					Store (F3PW,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+		}
+
+		PowerResource (FNP3, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 3)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				If (LNot (_STA ())) {
+					Store (3, \FLVL)
+					Store (F3PW,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+			Method (_OFF) {
+				If (_STA ()) {
+					Store (4, \FLVL)
+					Store (F4PW,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+		}
+
+		PowerResource (FNP4, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 4)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				If (LNot (_STA ())) {
+					Store (4, \FLVL)
+					Store (F4PW,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+			Method (_OFF) {
+				If (_STA ()) {
+					Store (4, \FLVL)
+					Store (F4PW,
+						\_SB.PCI0.LPCB.SIO.ENVC.F2PS)
+					Notify (\_TZ.THRM, 0x81)
+				}
+			}
+		}
+
+		Device (FAN0)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 0)
+			Name (_PR0, Package () { FNP0 })
+		}
+
+		Device (FAN1)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 1)
+			Name (_PR0, Package () { FNP1 })
+		}
+
+		Device (FAN2)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 2)
+			Name (_PR0, Package () { FNP2 })
+		}
+
+		Device (FAN3)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 3)
+			Name (_PR0, Package () { FNP3 })
+		}
+
+		Device (FAN4)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 4)
+			Name (_PR0, Package () { FNP4 })
+		}
+	}
+}
diff --git a/src/mainboard/google/jecht/variants/tidus/include/variant/gpio.h b/src/mainboard/google/jecht/variants/tidus/include/variant/gpio.h
new file mode 100644
index 0000000000..846fe816d4
--- /dev/null
+++ b/src/mainboard/google/jecht/variants/tidus/include/variant/gpio.h
@@ -0,0 +1,120 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef TIDUS_GPIO_H
+#define TIDUS_GPIO_H
+
+#include <soc/gpio.h>
+
+static const struct gpio_config mainboard_gpio_config[] = {
+	PCH_GPIO_UNUSED,        /* 0: UNUSED */
+	PCH_GPIO_UNUSED,        /* 1: UNUSED */
+	PCH_GPIO_UNUSED,        /* 2: UNUSED */
+	PCH_GPIO_UNUSED,        /* 3: UNUSED */
+	PCH_GPIO_NATIVE,        /* 4: NATIVE: I2C0_SDA_GPIO4 */
+	PCH_GPIO_NATIVE,        /* 5: NATIVE: I2C0_SCL_GPIO5 */
+	PCH_GPIO_NATIVE,        /* 6: NATIVE: I2C1_SDA_GPIO6 */
+	PCH_GPIO_NATIVE,        /* 7: NATIVE: I2C1_SCL_GPIO7 */
+	PCH_GPIO_ACPI_SCI,      /* 8: LAN_WAKE_L_Q */
+	PCH_GPIO_OUT_HIGH,      /* 9: PP3300_WLAN_EN */
+	PCH_GPIO_ACPI_SCI,      /* 10: WLAN_WAKE_L_Q */
+	PCH_GPIO_UNUSED,        /* 11: SMBALERT */
+	PCH_GPIO_INPUT_INVERT,  /* 12: RECOVERY_L */
+	PCH_GPIO_UNUSED,        /* 13: UNUSED */
+	PCH_GPIO_UNUSED,        /* 14: UNUSED */
+	PCH_GPIO_UNUSED,        /* 15: UNUSED (STRAP) */
+	PCH_GPIO_UNUSED,        /* 16: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 17: PP3300_VP8_EN */
+	PCH_GPIO_UNUSED,        /* 18: UNUSED */
+	PCH_GPIO_UNUSED,        /* 19: UNUSED */
+	PCH_GPIO_NATIVE,        /* 20: NATIVE: CLK_PCIE_REQ2# */
+	PCH_GPIO_NATIVE,        /* 21: NATIVE: CLK_PCIE_REQ3# */
+	PCH_GPIO_NATIVE,        /* 22: NATIVE: CLK_PCIE_REQ4# */
+	PCH_GPIO_UNUSED,        /* 23: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 24: WLAN_OFF_L */
+	PCH_GPIO_UNUSED,        /* 25: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 26: USB_CTL_1 */
+	PCH_GPIO_UNUSED,        /* 27: UNUSED */
+	PCH_GPIO_OUT_LOW,      /* 28: USB_ILIM_SEL */
+	PCH_GPIO_UNUSED,        /* 29: UNUSED */
+	PCH_GPIO_NATIVE,        /* 30: NATIVE: PCH_SUSPWRACK_L */
+	PCH_GPIO_NATIVE,        /* 31: NATIVE: PCH_ACPRESENT */
+	PCH_GPIO_NATIVE,        /* 32: NATIVE: CLKRUN# */
+	PCH_GPIO_NATIVE,        /* 33: NATIVE: DEVSLP0 */
+	PCH_GPIO_ACPI_SMI,      /* 34: EC_SMI_L */
+	PCH_GPIO_ACPI_SMI,      /* 35: PCH_NMI_DBG_L (route in NMI_EN) */
+	PCH_GPIO_ACPI_SCI,      /* 36: EC_SCI_L */
+	PCH_GPIO_UNUSED,        /* 37: UNUSED */
+	PCH_GPIO_UNUSED,        /* 38: UNUSED */
+	PCH_GPIO_UNUSED,        /* 39: UNUSED */
+	PCH_GPIO_NATIVE,        /* 40: NATIVE: USB_OC0# */
+	PCH_GPIO_NATIVE,        /* 41: NATIVE: USB_OC1# */
+	PCH_GPIO_NATIVE,        /* 42: NATIVE: USB_OC2# */
+	PCH_GPIO_NATIVE,        /* 43: NATIVE: USB_OC3# */
+	PCH_GPIO_UNUSED,        /* 44: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 45: PP5000_CODEC_EN */
+	PCH_GPIO_OUT_HIGH,      /* 46: BT_DISABLE_L */
+	PCH_GPIO_OUT_HIGH,      /* 47: USB1_PWR_EN */
+	PCH_GPIO_OUT_HIGH,      /* 48: USB4_PWR_EN */
+	PCH_GPIO_OUT_LOW,       /* 49: POWER_LED */
+	PCH_GPIO_OUT_HIGH,      /* 50: VP8_DISABLE_L */
+	PCH_GPIO_UNUSED,        /* 51: UNUSED */
+	PCH_GPIO_UNUSED,        /* 52: UNUSED */
+	PCH_GPIO_UNUSED,        /* 53: UNUSED */
+	PCH_GPIO_UNUSED,        /* 54: UNUSED */
+	PCH_GPIO_UNUSED,        /* 55: UNUSED */
+	PCH_GPIO_OUT_HIGH,      /* 56: USB2_PWR_EN */
+	PCH_GPIO_OUT_HIGH,      /* 57: USB3_PWR_EN */
+	PCH_GPIO_INPUT,         /* 58: PCH_SPI_WP_D */
+	PCH_GPIO_OUT_HIGH,      /* 59: PP3300_LAN_EN */
+	PCH_GPIO_NATIVE,        /* 60: NATIVE: SMB0ALERT# */
+	PCH_GPIO_UNUSED,        /* 61: UNUSED */
+	PCH_GPIO_UNUSED,        /* 62: UNUSED */
+	PCH_GPIO_NATIVE,        /* 63: NATIVE: PCH_SLP_S5_L */
+	PCH_GPIO_UNUSED,        /* 64: UNUSED */
+	PCH_GPIO_UNUSED,        /* 65: UNUSED */
+	PCH_GPIO_UNUSED,        /* 66: UNUSED (STRAP) */
+	PCH_GPIO_UNUSED,        /* 67: UNUSED */
+	PCH_GPIO_UNUSED,        /* 68: UNUSED */
+	PCH_GPIO_UNUSED,        /* 69: UNUSED */
+	PCH_GPIO_UNUSED,        /* 70: UNUSED */
+	PCH_GPIO_NATIVE,        /* 71: NATIVE: MODPHY_EN */
+	PCH_GPIO_UNUSED,        /* 72: UNUSED */
+	PCH_GPIO_UNUSED,        /* 73: UNUSED */
+	PCH_GPIO_NATIVE,        /* 74: NATIVE: SMB_ME1_DAT */
+	PCH_GPIO_NATIVE,        /* 75: NATIVE: SMB_ME1_CLK */
+	PCH_GPIO_UNUSED,        /* 76: UNUSED */
+	PCH_GPIO_UNUSED,        /* 77: UNUSED */
+	PCH_GPIO_UNUSED,        /* 78: UNUSED */
+	PCH_GPIO_UNUSED,        /* 79: UNUSED */
+	PCH_GPIO_UNUSED,        /* 80: UNUSED */
+	PCH_GPIO_NATIVE,        /* 81: NATIVE: SPKR */
+	PCH_GPIO_NATIVE,        /* 82: NATIVE: EC_RCIN_L */
+	PCH_GPIO_UNUSED,        /* 83: UNUSED */
+	PCH_GPIO_UNUSED,        /* 84: UNUSED */
+	PCH_GPIO_UNUSED,        /* 85: UNUSED */
+	PCH_GPIO_UNUSED,        /* 86: UNUSED (STRAP) */
+	PCH_GPIO_UNUSED,        /* 87: UNUSED */
+	PCH_GPIO_UNUSED,        /* 88: UNUSED */
+	PCH_GPIO_UNUSED,        /* 89: UNUSED */
+	PCH_GPIO_UNUSED,        /* 90: UNUSED */
+	PCH_GPIO_UNUSED,        /* 91: UNUSED */
+	PCH_GPIO_UNUSED,        /* 92: UNUSED */
+	PCH_GPIO_UNUSED,        /* 93: UNUSED */
+	PCH_GPIO_UNUSED,        /* 94: UNUSED */
+	PCH_GPIO_END
+};
+
+#endif
diff --git a/src/mainboard/google/jecht/variants/tidus/include/variant/thermal.h b/src/mainboard/google/jecht/variants/tidus/include/variant/thermal.h
new file mode 100644
index 0000000000..4236424a35
--- /dev/null
+++ b/src/mainboard/google/jecht/variants/tidus/include/variant/thermal.h
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef THERMAL_H
+#define THERMAL_H
+
+#define TEMPERATURE_SENSOR_ID		0	/* PECI */
+
+/* Thermal Policy 0 */
+/* Fan is at default speed */
+#define FAN4_0_PWM		0x4d
+
+/* Fan is at LOW speed */
+#define FAN3_0_THRESHOLD_OFF	62
+#define FAN3_0_THRESHOLD_ON	70
+#define FAN3_0_PWM		0x5e
+
+/* Fan is at MEDIUM speed */
+#define FAN2_0_THRESHOLD_OFF	68
+#define FAN2_0_THRESHOLD_ON	81
+#define FAN2_0_PWM		0x78
+
+/* Fan is at HIGH speed */
+#define FAN1_0_THRESHOLD_OFF	78
+#define FAN1_0_THRESHOLD_ON	91
+#define FAN1_0_PWM		0x93
+
+/* Fan is at FULL speed */
+#define FAN0_0_THRESHOLD_OFF	88
+#define FAN0_0_THRESHOLD_ON	100
+#define FAN0_0_PWM		0xb0
+
+/* Thermal Policy 1 */
+/* Fan is at default speed */
+#define FAN4_1_PWM		0x4d
+
+/* Fan is at LOW speed */
+#define FAN3_1_THRESHOLD_OFF	62
+#define FAN3_1_THRESHOLD_ON	70
+#define FAN3_1_PWM		0x5e
+
+/* Fan is at MEDIUM speed */
+#define FAN2_1_THRESHOLD_OFF	68
+#define FAN2_1_THRESHOLD_ON	81
+#define FAN2_1_PWM		0x70
+
+/* Fan is at HIGH speed */
+#define FAN1_1_THRESHOLD_OFF	78
+#define FAN1_1_THRESHOLD_ON	91
+#define FAN1_1_PWM		0x83
+
+/* Fan is at FULL speed */
+#define FAN0_1_THRESHOLD_OFF	88
+#define FAN0_1_THRESHOLD_ON	100
+#define FAN0_1_PWM		0x93
+
+/* Thermal Policy 2 */
+/* Fan is at default speed */
+#define FAN4_2_PWM		0x4d
+
+/* Fan is at LOW speed */
+#define FAN3_2_THRESHOLD_OFF	62
+#define FAN3_2_THRESHOLD_ON	70
+#define FAN3_2_PWM		0x59
+
+/* Fan is at MEDIUM speed */
+#define FAN2_2_THRESHOLD_OFF	68
+#define FAN2_2_THRESHOLD_ON	81
+#define FAN2_2_PWM		0x63
+
+/* Fan is at HIGH speed */
+#define FAN1_2_THRESHOLD_OFF	78
+#define FAN1_2_THRESHOLD_ON	91
+#define FAN1_2_PWM		0x6e
+
+/* Fan is at FULL speed */
+#define FAN0_2_THRESHOLD_OFF	88
+#define FAN0_2_THRESHOLD_ON	100
+#define FAN0_2_PWM		0x7e
+
+/* Threshold to change thermal policy */
+#define THERMAL_POLICY_0_THRESHOLD_OFF	38
+#define THERMAL_POLICY_0_THRESHOLD_ON	40
+
+#define THERMAL_POLICY_1_THRESHOLD_OFF	33
+#define THERMAL_POLICY_1_THRESHOLD_ON	35
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE		103
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE		105
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE			105
+
+#endif
diff --git a/src/mainboard/google/jecht/variants/tidus/pei_data.c b/src/mainboard/google/jecht/variants/tidus/pei_data.c
new file mode 100644
index 0000000000..7c03422553
--- /dev/null
+++ b/src/mainboard/google/jecht/variants/tidus/pei_data.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+	pei_data->ec_present = 0;
+
+	/* P0: VP8 */
+	pei_data_usb2_port(pei_data, 0, 0x0064, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_MINI_PCIE);
+	/* P1: Port 3, USB3 */
+	pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0,
+			   USB_PORT_INTERNAL);
+	/* P2: Port 4, USB4 */
+	pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1,
+			   USB_PORT_INTERNAL);
+	/* P3: Mini Card */
+	pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_MINI_PCIE);
+	/* P4: Port 1, USB1 */
+	pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2,
+			   USB_PORT_INTERNAL);
+	/* P5: Port 2, USB2 */
+	pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2,
+			   USB_PORT_INTERNAL);
+	/* P6: Card Reader */
+	pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
+			   USB_PORT_INTERNAL);
+	/* P7: Pin Header */
+	pei_data_usb2_port(pei_data, 7, 0x0040, 1, 3,
+			   USB_PORT_INTERNAL);
+
+	/* P1: USB1 */
+	pei_data_usb3_port(pei_data, 0, 1, 2, 0);
+	/* P2: USB2 */
+	pei_data_usb3_port(pei_data, 1, 1, 2, 0);
+	/* P3: USB3 */
+	pei_data_usb3_port(pei_data, 2, 1, 0, 0);
+	/* P4: USB4 */
+	pei_data_usb3_port(pei_data, 3, 1, 1, 0);
+}