diff options
| author | Shelley Chen <shchen@google.com> | 2022-01-05 17:15:31 -0800 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2022-01-07 22:27:37 +0000 |
| commit | 3538461468aa7b0b14e1c76e09f6104a3e551b4a (patch) | |
| tree | 5c84bf46cde001e1b96881f25f12abc27431f9cd /src/mainboard/google/herobrine/chromeos.c | |
| parent | f00680afc5df34bdc40fc7d1c43b4f1aa812fa13 (diff) | |
mb/google/herobrine: Initialize EC and TPM devices
Initialize EC and H1/TPM instances on herobrine devices.
BUG=b:182963902
BRANCH=None
TEST=Validated on qualcomm sc7280 development board
and verified booting on herobrine.
Change-Id: I8cbdd1d59a0166688d52d61646db1b6764879a7c
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/google/herobrine/chromeos.c')
| -rw-r--r-- | src/mainboard/google/herobrine/chromeos.c | 32 |
1 files changed, 29 insertions, 3 deletions
diff --git a/src/mainboard/google/herobrine/chromeos.c b/src/mainboard/google/herobrine/chromeos.c index 9faf4baf5f..4c37ef129c 100644 --- a/src/mainboard/google/herobrine/chromeos.c +++ b/src/mainboard/google/herobrine/chromeos.c @@ -3,9 +3,17 @@ #include <boot/coreboot_tables.h> #include <bootmode.h> #include "board.h" +#include <security/tpm/tis.h> void setup_chromeos_gpios(void) { + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + gpio_input_pullup(GPIO_EC_IN_RW); + gpio_input_pullup(GPIO_AP_EC_INT); + } + if (CONFIG(MAINBOARD_HAS_TPM2)) + gpio_input_irq(GPIO_H1_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP); + gpio_input_pullup(GPIO_SD_CD_L); if (CONFIG(HEROBRINE_HAS_FINGERPRINT)) { @@ -17,9 +25,19 @@ void setup_chromeos_gpios(void) void fill_lb_gpios(struct lb_gpios *gpios) { - struct lb_gpio chromeos_gpios[] = { + const struct lb_gpio chromeos_gpios[] = { {GPIO_SD_CD_L.addr, ACTIVE_LOW, gpio_get(GPIO_SD_CD_L), "SD card detect"}, +#if CONFIG(EC_GOOGLE_CHROMEEC) + {GPIO_EC_IN_RW.addr, ACTIVE_LOW, gpio_get(GPIO_EC_IN_RW), + "EC in RW"}, + {GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT), + "EC interrupt"}, +#endif +#if CONFIG(MAINBOARD_HAS_TPM2) + {GPIO_H1_AP_INT.addr, ACTIVE_HIGH, gpio_get(GPIO_H1_AP_INT), + "TPM interrupt"}, +#endif }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); @@ -27,6 +45,14 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_ec_is_trusted(void) { - /* Stub GPIO. */ - return 0; + /* EC is trusted if not in RW. This is active low. */ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + return !!gpio_get(GPIO_EC_IN_RW); + else /* If no EC, always return true */ + return 1; +} + +int tis_plat_irq_status(void) +{ + return gpio_irq_status(GPIO_H1_AP_INT); } |