mb/google/hatch/moonbuggy: Update GPIOs

Implement the GPIOs that have been changed from genesis.

- Connect scaler UART on pins C12/C13
- Connect the HDMI redriver I2C on C18/C19
- Connect the iMX8 signals on D1/D2/D3/D21/D22
- Connect the EC interrupt on D14 (same as on scout)
- Connect PCH_TYPEC_UPFB on E15 (same as on genesis)
- Configure as not connected the following unused pins: D23, E11, E12,
  F11 -> F22, H0, H8, H9

BUG=b:200876872
TEST=moonbuggy boots

Change-Id: Ie9cafe81e391bce6ab7ffbe23c2d57b407d146f3
Signed-off-by: Pablo Ceballos <pceballos@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

3 files changed, 59 insertions, 40 deletions

diff --git a/src/mainboard/google/hatch/variants/moonbuggy/gpio.c b/src/mainboard/google/hatch/variants/moonbuggy/gpio.c
index ba75fb768d..d8f392028d 100644
--- a/src/mainboard/google/hatch/variants/moonbuggy/gpio.c
+++ b/src/mainboard/google/hatch/variants/moonbuggy/gpio.c
@@ -33,65 +33,79 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
 	/* C1 : SMBDATA */
 	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
-	/* C3  : PCH_MBCLK1_R (i350) */
+	/* C3 : PCH_MBCLK1_R (i350) */
 	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
-	/* C4  : PCH_MBDAT1_R (i350) */
+	/* C4 : PCH_MBDAT1_R (i350) */
 	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
-	/* C6: M2_WLAN_WAKE_ODL */
+	/* C6 : M2_WLAN_WAKE_ODL */
 	PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE),
 	/* C7 : LAN_WAKE_ODL */
 	PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE),
 	/* C10 : PCH_PCON_RST_ODL */
 	PAD_CFG_GPO(GPP_C10, 1, DEEP),
-	/* C11 : PCH_PCON_PDB_ODL */
+	/* C11 : PCH_PCON1_PDB_ODL */
 	PAD_CFG_GPO(GPP_C11, 1, DEEP),
-	/* C15  : WLAN_OFF_L */
+	/* C12 : PCH_UART1_RX_ADB_TX */
+	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
+	/* C13 : PCH_UART1_TX_ADB_RX */
+	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
+	/* C15 : WLAN_OFF_L */
 	PAD_CFG_GPO(GPP_C15, 1, DEEP),
+	/* C16 : PCH_I2C_RFU_SDA (NC) */
+	PAD_NC(GPP_C16, NONE),
+	/* C17 : PCH_I2C_RFU_SCL (NC) */
+	PAD_NC(GPP_C17, NONE),
+	/* C18 : EC_I2C_HDMI_RE_SCL */
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	/* C19 : EC_12C_HDMI_RE_SDA */
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+
+	/* D1 : REC_MODE */
+	PAD_CFG_GPO(GPP_D1, 1, DEEP),
+	/* D2 : DEV_MODE_CTRL */
+	PAD_CFG_GPO(GPP_D2, 1, DEEP),
+	/* D3 : BOOT_IND */
+	PAD_CFG_GPI(GPP_D3, NONE, DEEP),
+	/* D14 : EC_PCH_INT_L */
+	PAD_CFG_GPI_APIC(GPP_D14, NONE, PLTRST, LEVEL, INVERT),
+	/* D21 : BOOT_SEL_N */
+	PAD_CFG_GPO(GPP_D21, 1, DEEP),
+	/* D22 : QSPI_MR_N */
+	PAD_CFG_GPO(GPP_D22, 1, DEEP),
+	/* D23 : Not connected */
+	PAD_NC(GPP_D23, NONE),
 
 	/* E2 : Not connected */
 	PAD_NC(GPP_E2, NONE),
-	/* E3 : TPU_RST_PIN40 */
+	/* E3 : TPU_BOOT_DELAY_PIN40 */
 	PAD_CFG_GPO(GPP_E3, 1, DEEP),
-	/* E7 : TPU_RST_PIN42 */
+	/* E7 : TPU_BOOT_DELAY_PIN42 */
 	PAD_CFG_GPO(GPP_E7, 1, DEEP),
 	/* E9 : PU 10K to PP3300_SOC_A */
 	PAD_NC(GPP_E9, NONE),
 	/* E10 : USB_A1_OC_ODL */
 	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
+	/* E11 : PU 10K to PP3300_SOC_A */
+	PAD_NC(GPP_E11, NONE),
+	/* E12 : PU 10K to PP3300_SOC_A */
+	PAD_NC(GPP_E12, NONE),
+	/* E15 : PCH_TYPEC_UPFB */
+	PAD_CFG_GPI(GPP_E15, NONE, DEEP),
 
-	/* F11 : EMMC_CMD */
-	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
-	/* F12 : EMMC_DATA0 */
-	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
-	/* F13 : EMMC_DATA1 */
-	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
-	/* F14 : EMMC_DATA2 */
-	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
-	/* F15 : EMMC_DATA3 */
-	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
-	/* F16 : EMMC_DATA4 */
-	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
-	/* F17 : EMMC_DATA5 */
-	PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
-	/* F18 : EMMC_DATA6 */
-	PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
-	/* F19 : EMMC_DATA7 */
-	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
-	/* F20 : EMMC_RCLK */
-	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
-	/* F21 : EMMC_CLK */
-	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
-	/* F22 : EMMC_RST_L */
-	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
-
-	/* H4: PCH_I2C_PCON_SDA */
+	/* H0 : Not connected */
+	PAD_NC(GPP_H0, NONE),
+	/* H4 : PCH_I2C_PCON_SDA */
 	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
-	/* H5: PCH_I2C_PCON_SCL */
+	/* H5 : PCH_I2C_PCON_SCL */
 	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
-	/* H6  : PCH_I2C_TPU_SDA */
+	/* H6 : PCH_I2C_TPU_SDA */
 	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
-	/* H7  : PCH_I2C_TPU_SCL */
+	/* H7 : PCH_I2C_TPU_SCL */
 	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	/* H8 : Not connected */
+	PAD_NC(GPP_H8, NONE),
+	/* H9 : Not connected */
+	PAD_NC(GPP_H9, NONE),
 	/* H22 : PWM_PP3300_BIOZZER */
 	PAD_CFG_GPO(GPP_H22, 0, DEEP),
 };
@@ -122,7 +136,7 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
 	/* C14 : BT_DISABLE_L */
 	PAD_CFG_GPO(GPP_C14, 0, DEEP),
-	/* PCH_WP_OD */
+	/* C20 : PCH_WP_OD */
 	PAD_CFG_GPI(GPP_C20, NONE, DEEP),
 	/* C21 : H1_PCH_INT_ODL */
 	PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
@@ -130,9 +144,9 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_GPI(GPP_C22, NONE, DEEP),
 	/* C23 : WLAN_PE_RST# */
 	PAD_CFG_GPO(GPP_C23, 1, DEEP),
-	/* E1  : M2_SSD_PEDET */
+	/* E1 : M2_SSD_PEDET */
 	PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
-	/* E5  : SATA_DEVSLP1 */
+	/* E5 : SATA_DEVSLP1 */
 	PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
 };
 
diff --git a/src/mainboard/google/hatch/variants/moonbuggy/include/variant/gpio.h b/src/mainboard/google/hatch/variants/moonbuggy/include/variant/gpio.h
index 79a141008f..9dd243400d 100644
--- a/src/mainboard/google/hatch/variants/moonbuggy/include/variant/gpio.h
+++ b/src/mainboard/google/hatch/variants/moonbuggy/include/variant/gpio.h
@@ -5,4 +5,7 @@
 
 #include <baseboard/gpio.h>
 
+#undef EC_SYNC_IRQ
+#define EC_SYNC_IRQ	GPP_D14_IRQ
+
 #endif
diff --git a/src/mainboard/google/hatch/variants/moonbuggy/overridetree.cb b/src/mainboard/google/hatch/variants/moonbuggy/overridetree.cb
index dd83f4d475..1049805700 100644
--- a/src/mainboard/google/hatch/variants/moonbuggy/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/moonbuggy/overridetree.cb
@@ -13,7 +13,7 @@ chip soc/intel/cannonlake
 		[PchSerialIoIndexSPI1] = PchSerialIoPci,
 		[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
 		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
-		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART1] = PchSerialIoPci,
 		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
 	}"
 
@@ -451,6 +451,8 @@ chip soc/intel/cannonlake
 		device pci 1d.5 on end # PCI Root Port 14 (non-root)
 		device pci 1d.6 on end # PCI Root Port 15 (non-root)
 		device pci 1d.7 on end # PCI Root Port 16 (non-root)
+		device pci 1e.0 on end # UART #0
+		device pci 1e.1 on end # UART #1
 		device pci 1e.3 off end # GSPI #1
 	end