mb/google/hatch: Add memory init setup for hatch

This implementation adds below support:

1. Add support to read memory strap.
2. Add support to configure below memory parameters
   -> rcomp resistor configuration
   -> dqs mapping
   -> ect and ca vref config
3. Include SPD configuration

BUG=b:120914069
BRANCH=None
TEST=USE="-intel_mrc -bmplk" emerge-hatch coreboot

Change-Id: I9bda08bd0b9f91ebb96b39291e15473492a6bf19
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30248
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

12 files changed, 241 insertions, 3 deletions

diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 24002022b6..ef060f5c3a 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -6,7 +6,6 @@ config BOARD_GOOGLE_BASEBOARD_HATCH
 	select DRIVERS_I2C_HID
 	select DRIVERS_SPI_ACPI
 	select EC_GOOGLE_CHROMEEC
-	select GENERIC_SPD_BIN
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select MAINBOARD_HAS_CHROMEOS
@@ -15,7 +14,6 @@ config BOARD_GOOGLE_BASEBOARD_HATCH
 	select SOC_INTEL_CANNONLAKE_MEMCFG_INIT
 	select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK
 	select SOC_INTEL_COFFEELAKE
-	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
 
 if BOARD_GOOGLE_BASEBOARD_HATCH
diff --git a/src/mainboard/google/hatch/Makefile.inc b/src/mainboard/google/hatch/Makefile.inc
index 54e42812e2..ca8c7f2b76 100644
--- a/src/mainboard/google/hatch/Makefile.inc
+++ b/src/mainboard/google/hatch/Makefile.inc
@@ -31,3 +31,5 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
 VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR))
 subdirs-y += variants/$(VARIANT_DIR)
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
+
+subdirs-y += spd
diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c
index b79feb8e1a..401f41f22b 100644
--- a/src/mainboard/google/hatch/romstage.c
+++ b/src/mainboard/google/hatch/romstage.c
@@ -13,8 +13,17 @@
  * GNU General Public License for more details.
  */
 
+#include <baseboard/variants.h>
+#include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	const struct spd_info spd = {
+		.spd_by_index = true,
+		.spd_spec.spd_index = variant_memory_sku(),
+	};
+
+	cannonlake_memcfg_init(&memupd->FspmConfig,
+			variant_memory_params(), &spd);
 }
diff --git a/src/mainboard/google/hatch/spd/Makefile.inc b/src/mainboard/google/hatch/spd/Makefile.inc
new file mode 100644
index 0000000000..e35544bc7d
--- /dev/null
+++ b/src/mainboard/google/hatch/spd/Makefile.inc
@@ -0,0 +1,34 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+SPD_BIN = $(obj)/spd.bin
+
+ifeq ($(SPD_SOURCES),)
+	SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this)
+else
+	SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+endif
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do printf $$(printf '\%o' 0x$$c); \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/hatch/spd/empty_ddr4.spd.hex b/src/mainboard/google/hatch/spd/empty_ddr4.spd.hex
new file mode 100644
index 0000000000..67b46cd239
--- /dev/null
+++ b/src/mainboard/google/hatch/spd/empty_ddr4.spd.hex
@@ -0,0 +1,32 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/hatch/spd/hynix_dimm_H5AN8G6NCJR-VKC-8GB.spd.hex b/src/mainboard/google/hatch/spd/hynix_dimm_H5AN8G6NCJR-VKC-8GB.spd.hex
new file mode 100644
index 0000000000..50506476fb
--- /dev/null
+++ b/src/mainboard/google/hatch/spd/hynix_dimm_H5AN8G6NCJR-VKC-8GB.spd.hex
@@ -0,0 +1,32 @@
+23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00
+00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A
+20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
+16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 87 2E
+0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80 AD 01 00 00 00 00 00 00 48 4D 41 38 35 31 53
+36 43 4A 52 36 4E 2D 56 4B 20 20 20 20 00 80 AD
+FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/hatch/spd/samsung_dimm_K4A4G165WE-BCRC-4GB.spd.hex b/src/mainboard/google/hatch/spd/samsung_dimm_K4A4G165WE-BCRC-4GB.spd.hex
new file mode 100644
index 0000000000..44196cfa96
--- /dev/null
+++ b/src/mainboard/google/hatch/spd/samsung_dimm_K4A4G165WE-BCRC-4GB.spd.hex
@@ -0,0 +1,32 @@
+23 11 0C 03 44 19 00 08 00 60 00 03 02 03 00 00
+00 00 07 0D F8 0F 00 00 6E 6E 6E 11 00 6E 20 08
+00 05 70 03 00 F0 2B 34 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
+16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C B5 00 00 00 00 E7 D6 BF 8D
+0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 35 36
+34 34 45 42 30 2D 43 52 43 20 20 20 20 00 80 CE
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/hatch/variants/baseboard/Makefile.inc b/src/mainboard/google/hatch/variants/baseboard/Makefile.inc
index dffacbbffa..182f283feb 100644
--- a/src/mainboard/google/hatch/variants/baseboard/Makefile.inc
+++ b/src/mainboard/google/hatch/variants/baseboard/Makefile.inc
@@ -1,6 +1,28 @@
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+SPD_SOURCES = samsung_dimm_K4A4G165WE-BCRC-4GB	# 0b000
+SPD_SOURCES += empty_ddr4	# 0b001
+SPD_SOURCES += empty_ddr4	# 0b010
+SPD_SOURCES += empty_ddr4	# 0b011
+SPD_SOURCES += empty_ddr4	# 0b100
+SPD_SOURCES += hynix_dimm_H5AN8G6NCJR-VKC-8GB	# 0b101
+
 bootblock-y += gpio.c
 
 romstage-y += gpio.c
+romstage-y += memory.c
 
 ramstage-y += gpio.c
 
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c
index d215b099e9..1c5504cecb 100644
--- a/src/mainboard/google/hatch/variants/baseboard/gpio.c
+++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c
@@ -39,6 +39,14 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPP_C20, NONE, DEEP),
 	/* EC_IN_RW_OD */
 	PAD_CFG_GPI(GPP_C22, NONE, DEEP),
+	/* PCH_MEM_STRAP0 */
+	PAD_CFG_GPI(GPP_F20, NONE, PLTRST),
+	/* PCH_MEM_STRAP1 */
+	PAD_CFG_GPI(GPP_F21, NONE, PLTRST),
+	/* PCH_MEM_STRAP2 */
+	PAD_CFG_GPI(GPP_F11, NONE, PLTRST),
+	/* PCH_MEM_STRAP3 */
+	PAD_CFG_GPI(GPP_F22, NONE, PLTRST),
 };
 
 const struct pad_config *__weak variant_gpio_table(size_t *num)
diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
index dc0ffeef4d..7191f39f5f 100644
--- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
@@ -22,4 +22,10 @@
 
 #define GPIO_PCH_WP	        GPP_C20
 
+/* Memory configuration board straps */
+#define GPIO_MEM_CONFIG_0	GPP_F20
+#define GPIO_MEM_CONFIG_1	GPP_F21
+#define GPIO_MEM_CONFIG_2	GPP_F11
+#define GPIO_MEM_CONFIG_3	GPP_F22
+
 #endif /* BASEBOARD_GPIO_H */
diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h
index 90a52c0c2f..038ec6e2c6 100644
--- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h
@@ -26,7 +26,10 @@ const struct pad_config *variant_gpio_table(size_t *num);
 const struct pad_config *variant_early_gpio_table(size_t *num);
 
 /* Return memory SKU for the board. */
-size_t variant_memory_sku(void);
+int variant_memory_sku(void);
+
+/* Return board specific memory configuration */
+const struct cnl_mb_cfg *variant_memory_params(void);
 
 /* Return ChromeOS gpio table and fill in number of entries. */
 const struct cros_gpio *variant_cros_gpios(size_t *num);
diff --git a/src/mainboard/google/hatch/variants/baseboard/memory.c b/src/mainboard/google/hatch/variants/baseboard/memory.c
new file mode 100644
index 0000000000..80f3ba4260
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/baseboard/memory.c
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <baseboard/gpio.h>
+#include <gpio.h>
+#include <soc/cnl_memcfg_init.h>
+
+static const struct cnl_mb_cfg baseboard_memcfg = {
+	/*
+	 * The dqs_map arrays map the ddr4 pins to the SoC pins
+	 * for both channels.
+	 *
+	 * the index = pin number on ddr4 part
+	 * the value = pin number on SoC
+	 */
+	.dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 },
+	.dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 },
+
+	/* Baseboard uses 120, 81 and 100 rcomp resistors */
+	.rcomp_resistor = { 120, 81, 100 },
+
+	/* Baseboard Rcomp target values */
+	.rcomp_targets = { 100, 40, 20, 20, 26 },
+
+	/* Set CaVref config to 2 */
+	.vref_ca_config = 2,
+
+	/* Enable Early Command Training */
+	.ect = 1,
+};
+
+const struct cnl_mb_cfg *__weak variant_memory_params(void)
+{
+	return &baseboard_memcfg;
+}
+
+int __weak variant_memory_sku(void)
+{
+	const gpio_t spd_gpios[] = {
+		GPIO_MEM_CONFIG_0,
+		GPIO_MEM_CONFIG_1,
+		GPIO_MEM_CONFIG_2,
+		GPIO_MEM_CONFIG_3,
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}