diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-10-02 18:28:22 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-13 17:32:37 +0000 |
| commit | a1843d8411d3caebd0600421c2b6a4c6b0588c19 (patch) | |
| tree | d1baeb97ea1ca28ca09df0ceb3edd53ef0eea029 /src/mainboard/google/hatch | |
| parent | 8a64ad09a100adf478d65e42e4cc10a18ccc2d16 (diff) | |
soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig
Select `PM_ACPI_TIMER_OPTIONAL` to enable the new PM ACPI Kconfig and
set the FSP option for PM ACPI timer enablement from its value instead
of using the old devicetree option.
Also drop the obsolete devicetree option from soc code and from the
mainboards and add a corresponding Kconfig entry instead.
Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45955
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/hatch')
| -rw-r--r-- | src/mainboard/google/hatch/Kconfig | 3 | ||||
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 2 |
2 files changed, 3 insertions, 2 deletions
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 1e132ed0fd..4d7d5ec990 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -186,4 +186,7 @@ config VBOOT select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN select VBOOT_EARLY_EC_SYNC +config USE_PM_ACPI_TIMER + default n + endif # BOARD_GOOGLE_HATCH_COMMON diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 01c0d234f9..31f6652401 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -53,8 +53,6 @@ chip soc/intel/cannonlake # putting it under register "common_soc_config" in overridetree.cb file. register "common_soc_config.pch_thermal_trip" = "77" - register "PmTimerDisabled" = "1" - # Select CPU PL2/PL4 config register "cpu_pl2_4_cfg" = "baseline" |