mb/google/hatch: do UART pad configuration at board-level

UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: I62ffbe36bd7b7675aa0f41a8c6e9214d04ad4ae5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49428
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

12 files changed, 45 insertions, 6 deletions

diff --git a/src/mainboard/google/hatch/bootblock.c b/src/mainboard/google/hatch/bootblock.c
index 041ffcffd2..6e2f34d10e 100644
--- a/src/mainboard/google/hatch/bootblock.c
+++ b/src/mainboard/google/hatch/bootblock.c
@@ -4,7 +4,7 @@
 #include <bootblock_common.h>
 #include <soc/gpio.h>
 
-static void early_config_gpio(void)
+void bootblock_mainboard_early_init(void)
 {
 	const struct pad_config *variant_early_table;
 	size_t variant_gpios;
@@ -12,8 +12,3 @@ static void early_config_gpio(void)
 	variant_early_table = variant_early_gpio_table(&variant_gpios);
 	gpio_configure_pads(variant_early_table, variant_gpios);
 }
-
-void bootblock_mainboard_init(void)
-{
-	early_config_gpio();
-}
diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c
index 7694b0c930..b08f062186 100644
--- a/src/mainboard/google/hatch/variants/akemi/gpio.c
+++ b/src/mainboard/google/hatch/variants/akemi/gpio.c
@@ -152,6 +152,10 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
 	/* B18 : H1_SLAVE_SPI_MOSI_R */
 	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+	/* C8  : UART_PCH_RX_DEBUG_TX */
+	PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+	/* C9  : UART_PCH_TX_DEBUG_RX */
+	PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
 	/* C14 : BT_DISABLE_L */
 	PAD_CFG_GPO(GPP_C14, 0, DEEP),
 	/* PCH_WP_OD */
diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c
index f50f8f23a0..32591b82bf 100644
--- a/src/mainboard/google/hatch/variants/dratini/gpio.c
+++ b/src/mainboard/google/hatch/variants/dratini/gpio.c
@@ -78,6 +78,10 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
 	/* B18 : H1_SLAVE_SPI_MOSI_R */
 	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+	/* C8  : UART_PCH_RX_DEBUG_TX */
+	PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+	/* C9  : UART_PCH_TX_DEBUG_RX */
+	PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
 	/* C14 : BT_DISABLE_L */
 	PAD_CFG_GPO(GPP_C14, 0, DEEP),
 	/* PCH_WP_OD */
diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c
index 5870261cbb..cfd324892d 100644
--- a/src/mainboard/google/hatch/variants/hatch/gpio.c
+++ b/src/mainboard/google/hatch/variants/hatch/gpio.c
@@ -50,6 +50,10 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
 	/* B18 : H1_SLAVE_SPI_MOSI_R */
 	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+	/* C8  : UART_PCH_RX_DEBUG_TX */
+	PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+	/* C9  : UART_PCH_TX_DEBUG_RX */
+	PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
 	/* C14 : BT_DISABLE_L */
 	PAD_CFG_GPO(GPP_C14, 0, DEEP),
 	/* PCH_WP_OD */
diff --git a/src/mainboard/google/hatch/variants/helios/gpio.c b/src/mainboard/google/hatch/variants/helios/gpio.c
index 1c4f862a9a..9885802140 100644
--- a/src/mainboard/google/hatch/variants/helios/gpio.c
+++ b/src/mainboard/google/hatch/variants/helios/gpio.c
@@ -114,6 +114,10 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
 	/* B18 : H1_SLAVE_SPI_MOSI_R */
 	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+	/* C8  : UART_PCH_RX_DEBUG_TX */
+	PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+	/* C9  : UART_PCH_TX_DEBUG_RX */
+	PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
 	/* C14 : BT_DISABLE_L */
 	PAD_CFG_GPO(GPP_C14, 0, DEEP),
 	/* PCH_WP_OD */
diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c
index 4029f062db..a0658b091a 100644
--- a/src/mainboard/google/hatch/variants/jinlon/gpio.c
+++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c
@@ -80,6 +80,10 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
 	/* B18 : H1_SLAVE_SPI_MOSI_R */
 	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+	/* C8  : UART_PCH_RX_DEBUG_TX */
+	PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+	/* C9  : UART_PCH_TX_DEBUG_RX */
+	PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
 	/* C14 : BT_DISABLE_L */
 	PAD_CFG_GPO(GPP_C14, 0, DEEP),
 	/* PCH_WP_OD */
diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c
index 8073e095bf..b147e41118 100644
--- a/src/mainboard/google/hatch/variants/kindred/gpio.c
+++ b/src/mainboard/google/hatch/variants/kindred/gpio.c
@@ -210,6 +210,10 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
 	/* B18 : H1_SLAVE_SPI_MOSI_R */
 	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+	/* C8  : UART_PCH_RX_DEBUG_TX */
+	PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+	/* C9  : UART_PCH_TX_DEBUG_RX */
+	PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
 	/* C14 : BT_DISABLE_L */
 	PAD_CFG_GPO(GPP_C14, 0, DEEP),
 	/* PCH_WP_OD */
diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c
index 6a3d0da428..d45e9cb0ff 100644
--- a/src/mainboard/google/hatch/variants/kohaku/gpio.c
+++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c
@@ -96,6 +96,10 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
 	/* B18 : H1_SLAVE_SPI_MOSI_R */
 	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+	/* C8  : UART_PCH_RX_DEBUG_TX */
+	PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+	/* C9  : UART_PCH_TX_DEBUG_RX */
+	PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
 	/* C14 : BT_DISABLE_L */
 	PAD_CFG_GPO(GPP_C14, 0, DEEP),
 	/* PCH_WP_OD */
diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c
index e421a1a2fd..582d68e6a2 100644
--- a/src/mainboard/google/hatch/variants/mushu/gpio.c
+++ b/src/mainboard/google/hatch/variants/mushu/gpio.c
@@ -54,6 +54,10 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
 	/* B18 : H1_SLAVE_SPI_MOSI_R */
 	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+	/* C8  : UART_PCH_RX_DEBUG_TX */
+	PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+	/* C9  : UART_PCH_TX_DEBUG_RX */
+	PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
 	/* C14 : BT_DISABLE_L */
 	PAD_CFG_GPO(GPP_C14, 0, DEEP),
 	/* PCH_WP_OD */
diff --git a/src/mainboard/google/hatch/variants/nightfury/gpio.c b/src/mainboard/google/hatch/variants/nightfury/gpio.c
index eb6217ded9..1ab10a84af 100644
--- a/src/mainboard/google/hatch/variants/nightfury/gpio.c
+++ b/src/mainboard/google/hatch/variants/nightfury/gpio.c
@@ -110,6 +110,10 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
 	/* B18 : H1_SLAVE_SPI_MOSI_R */
 	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+	/* C8  : UART_PCH_RX_DEBUG_TX */
+	PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+	/* C9  : UART_PCH_TX_DEBUG_RX */
+	PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
 	/* C14 : BT_DISABLE_L */
 	PAD_CFG_GPO(GPP_C14, 0, DEEP),
 	/* PCH_WP_OD */
diff --git a/src/mainboard/google/hatch/variants/palkia/gpio.c b/src/mainboard/google/hatch/variants/palkia/gpio.c
index 3675375b28..c4d6f50dd7 100644
--- a/src/mainboard/google/hatch/variants/palkia/gpio.c
+++ b/src/mainboard/google/hatch/variants/palkia/gpio.c
@@ -118,6 +118,10 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
 	/* B18 : H1_SLAVE_SPI_MOSI_R */
 	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+	/* C8  : UART_PCH_RX_DEBUG_TX */
+	PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+	/* C9  : UART_PCH_TX_DEBUG_RX */
+	PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
 	/* C14 : BT_DISABLE_L */
 	PAD_CFG_GPO(GPP_C14, 0, DEEP),
 	/* PCH_WP_OD */
diff --git a/src/mainboard/google/hatch/variants/stryke/gpio.c b/src/mainboard/google/hatch/variants/stryke/gpio.c
index 6629e76d6b..fd8a55c09d 100644
--- a/src/mainboard/google/hatch/variants/stryke/gpio.c
+++ b/src/mainboard/google/hatch/variants/stryke/gpio.c
@@ -70,6 +70,10 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
 	/* B18 : H1_SLAVE_SPI_MOSI_R */
 	PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+	/* C8  : UART_PCH_RX_DEBUG_TX */
+	PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
+	/* C9  : UART_PCH_TX_DEBUG_RX */
+	PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
 	/* C14 : BT_DISABLE_L */
 	PAD_CFG_GPO(GPP_C14, 0, DEEP),
 	/* PCH_WP_OD */