diff options
| author | Furquan Shaikh <furquan@google.com> | 2019-03-11 20:22:59 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2019-03-13 15:49:12 +0000 |
| commit | 7418464c06203aafd1b8c47e22a6b5f1e8a41c14 (patch) | |
| tree | 3003e099478fcbaeedc6b2a10ef0b7d2c63d5c58 /src/mainboard/google/hatch | |
| parent | 5c19009ec710387a00df5760468b882079701432 (diff) | |
mb/google/hatch: Provide DRAM part number from EEPROM
This change reads DRAM part number from EEPROM if available and
returns it using the SoC callback (mainboard_get_dram_part_number).
BUG=b:127609572
TEST=Verify that DRAM part number from EEPROM is added to DMI table
17 (dmidecode -t 17).
Change-Id: I6ade6999828b6d67aa78d04199138f195a97ba8c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/hatch')
| -rw-r--r-- | src/mainboard/google/hatch/romstage.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c index 401f41f22b..429aa09d8f 100644 --- a/src/mainboard/google/hatch/romstage.c +++ b/src/mainboard/google/hatch/romstage.c @@ -14,8 +14,12 @@ */ #include <baseboard/variants.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <memory_info.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> +#include <string.h> void mainboard_memory_init_params(FSPM_UPD *memupd) { @@ -27,3 +31,29 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) cannonlake_memcfg_init(&memupd->FspmConfig, variant_memory_params(), &spd); } + +void mainboard_get_dram_part_num(const char **part_num, size_t *len) +{ + static char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; + static enum { + PART_NUM_NOT_READ, + PART_NUM_AVAILABLE, + PART_NUM_NOT_IN_CBI, + } part_num_state = PART_NUM_NOT_READ; + + if (part_num_state == PART_NUM_NOT_READ) { + if (google_chromeec_cbi_get_dram_part_num(&part_num_store[0], + sizeof(part_num_store)) < 0) { + printk(BIOS_ERR, "No DRAM part number in CBI!\n"); + part_num_state = PART_NUM_NOT_IN_CBI; + } else { + part_num_state = PART_NUM_AVAILABLE; + } + } + + if (part_num_state == PART_NUM_NOT_IN_CBI) + return; + + *part_num = &part_num_store[0]; + *len = strlen(part_num_store) + 1; +} |