mainboard/google/hatch: Move gpio GPP_H3 config up from baseboard

The baseboard GPIO table definitions are too straineous to the extend
that variants need to redefine assumptions back to NC. Invert this so
that baseboard by default assumes the safer NC and move the specific
board configurations to their respective places.

This patch handles the GPP_H3 gpio config for easier review. This
toggles the MAX amp which not all boards have. Move the pin
configuration to boards with the respective devicetree configuration
following on from the theme of commit b417786525.

BUG=b:142094759
BRANCH=none
TEST=builds

Change-Id: Iefd2223af79a13c8a42d07bc10b2772dbff6d3e5
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

8 files changed, 20 insertions, 2 deletions

diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c
index 0e3e46feb8..cfc185e9a5 100644
--- a/src/mainboard/google/hatch/variants/akemi/gpio.c
+++ b/src/mainboard/google/hatch/variants/akemi/gpio.c
@@ -122,6 +122,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
 	/* F22 : EMMC_RESET# ==> EMMC_RST_L */
 	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+	/* H3  : SPKR_PA_EN */
+	PAD_CFG_GPO(GPP_H3, 0, DEEP),
 	/* H6  : NC */
 	PAD_NC(GPP_H6, NONE),
 	/* H7  : NC */
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c
index 2c3bf8d546..dcd987fbb4 100644
--- a/src/mainboard/google/hatch/variants/baseboard/gpio.c
+++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c
@@ -334,8 +334,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3),
 	/* H2  : CNV_CLKREQ0 */
 	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
-	/* H3  : SPKR_PA_EN */
-	PAD_CFG_GPO(GPP_H3, 0, DEEP),
+	/* H3 : GPP_H3 ==> NC */
+	PAD_NC(GPP_H3, NONE),
 	/* H4  : PCH_I2C_PEN_SDA */
 	PAD_NC(GPP_H4, NONE),
 	/* H5  : PCH_I2C_PEN_SCL */
diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c
index 204715b216..fd59060756 100644
--- a/src/mainboard/google/hatch/variants/dratini/gpio.c
+++ b/src/mainboard/google/hatch/variants/dratini/gpio.c
@@ -59,6 +59,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
 	/* F22 : EMMC_RESET# ==> EMMC_RST_L */
 	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+	/* H3  : SPKR_PA_EN */
+	PAD_CFG_GPO(GPP_H3, 0, DEEP),
 	/* H19 : MEM_STRAP_0 */
 	PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
 	/* H22 : MEM_STRAP_1 */
diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c
index 7d2ecf279c..12d96d8496 100644
--- a/src/mainboard/google/hatch/variants/jinlon/gpio.c
+++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c
@@ -59,6 +59,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F21, NONE),
 	/* F22 : EMMC_RESET# ==> NC */
 	PAD_NC(GPP_F22, NONE),
+	/* H3  : SPKR_PA_EN */
+	PAD_CFG_GPO(GPP_H3, 0, DEEP),
 	/* H19 : MEM_STRAP_0 */
 	PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
 	/* H22 : MEM_STRAP_1 */
diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c
index 19956b4f1e..fbb47f95de 100644
--- a/src/mainboard/google/hatch/variants/kindred/gpio.c
+++ b/src/mainboard/google/hatch/variants/kindred/gpio.c
@@ -65,6 +65,8 @@ static const struct pad_config ssd_sku_gpio_table[] = {
 	PAD_NC(GPP_F21, NONE),
 	/* F22 : EMMC_RESET# ==> NC */
 	PAD_NC(GPP_F22, NONE),
+	/* H3  : SPKR_PA_EN */
+	PAD_CFG_GPO(GPP_H3, 0, DEEP),
 	/* H19 : MEM_STRAP_0 */
 	PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
 	/* H22 : MEM_STRAP_1 */
@@ -124,6 +126,8 @@ static const struct pad_config emmc_sku_gpio_table[] = {
 	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
 	/* F22 : EMMC_RESET# ==> EMMC_RST_L */
 	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+	/* H3  : SPKR_PA_EN */
+	PAD_CFG_GPO(GPP_H3, 0, DEEP),
 	/* H19 : MEM_STRAP_0 */
 	PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
 	/* H22 : MEM_STRAP_1 */
@@ -177,6 +181,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
 	/* F22 : EMMC_RESET# ==> EMMC_RST_L */
 	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+	/* H3  : SPKR_PA_EN */
+	PAD_CFG_GPO(GPP_H3, 0, DEEP),
 	/* H19 : MEM_STRAP_0 */
 	PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
 	/* H22 : MEM_STRAP_1 */
diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c
index 837abb3e8b..8fd203d18d 100644
--- a/src/mainboard/google/hatch/variants/kohaku/gpio.c
+++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c
@@ -77,6 +77,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_G5, NONE),
 	/* G6 : GPP_G6 ==> NC  */
 	PAD_NC(GPP_G6, NONE),
+	/* H3  : SPKR_PA_EN */
+	PAD_CFG_GPO(GPP_H3, 0, DEEP),
 	/* H4  : PCH_I2C_PEN_SDA */
 	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
 	/* H5  : PCH_I2C_PEN_SCL */
diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c
index 862b28fe4a..09e159492c 100644
--- a/src/mainboard/google/hatch/variants/mushu/gpio.c
+++ b/src/mainboard/google/hatch/variants/mushu/gpio.c
@@ -39,6 +39,8 @@ static const struct pad_config gpio_table[] = {
 	 * using this pin, expose this pin to driver.
 	 */
 	PAD_CFG_GPO(GPP_C15, 1, DEEP),
+	/* H3  : SPKR_PA_EN */
+	PAD_CFG_GPO(GPP_H3, 0, DEEP),
 };
 
 const struct pad_config *override_gpio_table(size_t *num)
diff --git a/src/mainboard/google/hatch/variants/stryke/gpio.c b/src/mainboard/google/hatch/variants/stryke/gpio.c
index 4d0eba9ed1..82ffb6cb61 100644
--- a/src/mainboard/google/hatch/variants/stryke/gpio.c
+++ b/src/mainboard/google/hatch/variants/stryke/gpio.c
@@ -53,6 +53,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_F21, NONE),
 	/* F22 : NC */
 	PAD_NC(GPP_F22, NONE),
+	/* H3  : SPKR_PA_EN */
+	PAD_CFG_GPO(GPP_H3, 0, DEEP),
 	/* H19 : MEM_STRAP_0 */
 	PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
 	/* H22 : MEM_STRAP_1 */