diff options
| author | Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> | 2021-08-05 11:32:15 +0800 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2021-08-10 21:15:44 +0000 |
| commit | bde3c56d2cd0fc117d8ab9a51e8b67ba0b73d090 (patch) | |
| tree | 497b55ab16cd80e474c9e14519cbcfe606ce66b2 /src/mainboard/google/hatch/variants | |
| parent | 0c78fffa54d54249854f83b4711c587e007e85ea (diff) | |
mb/google/hatch/scout: Update DPTF parameters
update the DPTF parameters received from the thermal team.
BUG=b:195602767
TEST=emerge-ambassador coreboot
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: I5dc89d1d4c2b64c9aac780a7db743a91fd0ebc9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56819
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Jeff Chase <jnchase@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/hatch/variants')
| -rw-r--r-- | src/mainboard/google/hatch/variants/scout/overridetree.cb | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/src/mainboard/google/hatch/variants/scout/overridetree.cb b/src/mainboard/google/hatch/variants/scout/overridetree.cb index a6e115081b..8b7d558b47 100644 --- a/src/mainboard/google/hatch/variants/scout/overridetree.cb +++ b/src/mainboard/google/hatch/variants/scout/overridetree.cb @@ -240,20 +240,22 @@ chip soc/intel/cannonlake register "policies.active[0]" = "{.target=DPTF_CPU, .thresholds={TEMP_PCT(94, 0),}}" register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, - .thresholds={TEMP_PCT(72, 90), - TEMP_PCT(68, 80), - TEMP_PCT(62, 70), - TEMP_PCT(54, 60), - TEMP_PCT(46, 50), - TEMP_PCT(39, 40),}}" + .thresholds={TEMP_PCT(84, 90), + TEMP_PCT(82, 80), + TEMP_PCT(80, 70), + TEMP_PCT(66, 60), + TEMP_PCT(52, 50), + TEMP_PCT(35, 40),}}" ## Passive Policy register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 5000)" + register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 5000)" ## Critical Policy register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN)" + register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 90, SHUTDOWN)" ## Power Limits Control # PL1 is fixed at 15W, avg over 28-32s interval |