summaryrefslogtreecommitdiff
path: root/src/mainboard/google/hatch/variants/wyvern/overridetree.cb
diff options
context:
space:
mode:
authorFelix Singer <felix.singer@secunet.com>2020-08-04 16:47:10 +0200
committerMichael Niewöhner <c0d3z3r0@review.coreboot.org>2020-08-07 20:35:29 +0000
commit3de90d134494203556a81c47a6640ae101674114 (patch)
tree85ec6d856aeba4da218ea3ae5038565eab6bbd89 /src/mainboard/google/hatch/variants/wyvern/overridetree.cb
parentb7594b09b597075b3072e12c8338ca0cee66c006 (diff)
soc/intel/cnl: Set Heci1Disable depending on devicetree config
Currently HECI1 gets enabled by the option HeciEnabled, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement/disablement of the HECI1 device. All corresponding mainboards were checked if the devicetree matches the HeciEnabled setting, and adjusted where necessary. Change-Id: I03dd3577fbe3f68b0abc2d196d016a4d26d88ce5 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
Diffstat (limited to 'src/mainboard/google/hatch/variants/wyvern/overridetree.cb')
-rw-r--r--src/mainboard/google/hatch/variants/wyvern/overridetree.cb3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb
index c394977f6e..d7b2298a06 100644
--- a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/wyvern/overridetree.cb
@@ -1,6 +1,4 @@
chip soc/intel/cannonlake
- # Enable heci communication
- register "HeciEnabled" = "1"
# Auto-switch between X4 NVMe and X2 NVMe.
register "TetonGlacierMode" = "1"
@@ -303,6 +301,7 @@ chip soc/intel/cannonlake
device i2c 4a on end
end
end # I2C #3, Realtek RTD2142.
+ device pci 16.0 on end # Management Engine Interface 1
device pci 19.0 on
chip drivers/i2c/generic
register "hid" = ""10EC5682""