diff options
author | Bob Moragues <moragues@google.com> | 2019-12-06 14:20:00 -0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-19 17:46:19 +0000 |
commit | f82fa746bf9f5e07919f19563a9a0f2e136e40fe (patch) | |
tree | ab7913f07413ceb88f307ac0079a5f6d691ae1f7 /src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h | |
parent | bd3037bfa70e2a0ccc1e7a7c89353bcb6491d527 (diff) |
mb/google/hatch: Add mushu variant
Create initial overlays and build for mushu
Signed-off-by: Bob Moragues <moragues@chromium.org>
Change-Id: I81b5bf960ead0463159ac35f4f96e3ccc8c0364e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h')
-rw-r--r-- | src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h b/src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h new file mode 100644 index 0000000000..29e590422f --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_F20 +#define GPIO_MEM_CONFIG_1 GPP_F21 +#define GPIO_MEM_CONFIG_2 GPP_F11 +#define GPIO_MEM_CONFIG_3 GPP_F22 + +#endif |