diff options
| author | Edward O'Callaghan <quasisec@google.com> | 2019-12-24 15:15:35 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2019-12-25 07:16:23 +0000 |
| commit | 3dbe593906d22ddcd113cad9065b38115d0163a6 (patch) | |
| tree | 16d17dc69a9833d6a34cb7d353f716a84a9034b2 /src/mainboard/google/hatch/variants/jinlon | |
| parent | c4a3f51618a7575628fb513133952ac57326fc24 (diff) | |
mainboard/google/hatch: Move gpio GPP_C* NC down into baseboard
The baseboard GPIO table definitions are too straineous to the extend
that variants need to redefine assumptions back to NC. Invert this so
that baseboard by default assumes the safer NC and move the specific
board configurations to their respective places.
This patch handles the GPP_C15 group for easier review.
BUG=b:142094759
BRANCH=none
TEST=builds
Change-Id: I578245e24895d361d80ad016a4f18204e2b6e1ca
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/hatch/variants/jinlon')
| -rw-r--r-- | src/mainboard/google/hatch/variants/jinlon/gpio.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 3cf2c9d13e..7d2ecf279c 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -25,6 +25,12 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_A12, 0, DEEP), /* C12 : FPMCU_PCH_BOOT1 */ PAD_CFG_GPO(GPP_C12, 0, DEEP), + /* C15 : WWAN_DPR_SAR_ODL + * + * TODO: Driver doesn't use this pin as of now. In case driver starts + * using this pin, expose this pin to driver. + */ + PAD_CFG_GPO(GPP_C15, 1, DEEP), /* F3 : MEM_STRAP_3 */ PAD_CFG_GPI(GPP_F3, NONE, PLTRST), /* F10 : MEM_STRAP_2 */ |