diff options
| author | Wisley Chen <wisley.chen@quantatw.com> | 2019-12-19 17:16:42 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-26 10:41:41 +0000 |
| commit | f814ff15f977bbb409d944dfad687573ac3672b2 (patch) | |
| tree | 1d9ad85c219fe453e9bc3525e6e32b8ac53282f7 /src/mainboard/google/hatch/variants/jinlon/overridetree.cb | |
| parent | 1f7a11699a40b03162816ab2acd766c21aa24e8d (diff) | |
mb/google/hatch/var/jinlon: Update DPTF parameters
The change applies the DPTF parameters received from the thermal team.
BUG=b:146540028
TEST=build and verified by thermal team.
Change-Id: I222bac5f04ba5cdde1788c6d4ca8af80d323ca98
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/hatch/variants/jinlon/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/hatch/variants/jinlon/overridetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb index fd2861e5f6..c9613d2677 100644 --- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -1,4 +1,6 @@ chip soc/intel/cannonlake + register "tdp_pl1_override" = "15" + register "tdp_pl2_override" = "51" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, |