diff options
| author | Paul Fagerburg <pfagerburg@chromium.org> | 2019-06-13 14:38:08 -0600 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2019-06-13 22:29:10 +0000 |
| commit | 6440cb6945df740648ab3193a7d2025527b84522 (patch) | |
| tree | 1216bfbd2a1eaaf8700941bbf16c566af0389f3d /src/mainboard/google/hatch/variants/helios/Makefile.inc | |
| parent | 6ff848aaf811789460f7bf6f0f89f71aa7fe8bee (diff) | |
mb/google/hatch/variants/helios: Use LPDDR3 memory
Change the SPD makefile to use the LPDDR3 SPDs. Set up the arrays
for mapping SoC DQS pins to LPDDR3 pins.
BRANCH=none
BUG=b:133455595
TEST=`FEATURES="noclean" FW_NAME="helios" emerge-hatch chromeos-ec
depthcharge vboot_reference libpayload coreboot-private-files
intel-cmlfsp coreboot-private-files-hatch coreboot chromeos-bootimage`
Ensure the firmware builds without error.
Change-Id: Iebaba2ec65dfcf36674b4733b421ada107b22b09
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33456
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/hatch/variants/helios/Makefile.inc')
| -rw-r--r-- | src/mainboard/google/hatch/variants/helios/Makefile.inc | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/src/mainboard/google/hatch/variants/helios/Makefile.inc b/src/mainboard/google/hatch/variants/helios/Makefile.inc index cf6ee5ac97..ddafa3297f 100644 --- a/src/mainboard/google/hatch/variants/helios/Makefile.inc +++ b/src/mainboard/google/hatch/variants/helios/Makefile.inc @@ -12,9 +12,7 @@ ## GNU General Public License for more details. ## -SPD_SOURCES = 4G_2400 # 0b000 -SPD_SOURCES += empty_ddr4 # 0b001 -SPD_SOURCES += 8G_2400 # 0b010 -SPD_SOURCES += 8G_2666 # 0b011 -SPD_SOURCES += 16G_2400 # 0b100 -SPD_SOURCES += 16G_2666 # 0b101 +SPD_SOURCES = LP_8G_2133 # 0b0000 +SPD_SOURCES += LP_16G_2133 # 0b0001 + +romstage-y += memory.c |