diff options
author | Aamir Bohra <aamir.bohra@intel.com> | 2018-12-16 13:10:58 +0530 |
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committer | Subrata Banik <subrata.banik@intel.com> | 2018-12-23 05:12:14 +0000 |
commit | 4b85d46170ef44ab88b9cf844e3d3feaf9e7e89e (patch) | |
tree | 23405bc1cbb8224ed4043e5a90a837b4966ea633 /src/mainboard/google/hatch/variants/baseboard/gpio.c | |
parent | 09e7b998379225fb0b79e5fd2fb5ba9b95bd6961 (diff) |
mb/google/hatch: Add memory init setup for hatch
This implementation adds below support:
1. Add support to read memory strap.
2. Add support to configure below memory parameters
-> rcomp resistor configuration
-> dqs mapping
-> ect and ca vref config
3. Include SPD configuration
BUG=b:120914069
BRANCH=None
TEST=USE="-intel_mrc -bmplk" emerge-hatch coreboot
Change-Id: I9bda08bd0b9f91ebb96b39291e15473492a6bf19
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30248
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/hatch/variants/baseboard/gpio.c')
-rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/gpio.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index d215b099e9..1c5504cecb 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -39,6 +39,14 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* EC_IN_RW_OD */ PAD_CFG_GPI(GPP_C22, NONE, DEEP), + /* PCH_MEM_STRAP0 */ + PAD_CFG_GPI(GPP_F20, NONE, PLTRST), + /* PCH_MEM_STRAP1 */ + PAD_CFG_GPI(GPP_F21, NONE, PLTRST), + /* PCH_MEM_STRAP2 */ + PAD_CFG_GPI(GPP_F11, NONE, PLTRST), + /* PCH_MEM_STRAP3 */ + PAD_CFG_GPI(GPP_F22, NONE, PLTRST), }; const struct pad_config *__weak variant_gpio_table(size_t *num) |