diff options
| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2018-12-25 13:21:03 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-12-28 06:39:14 +0000 |
| commit | 8f537442d5d1014e333ed469d0e75a87f12cfbaf (patch) | |
| tree | bc77defdf503e0aac59c1ab25718ab897fd303ed /src/mainboard/google/hatch/variants/baseboard/devicetree.cb | |
| parent | 3b1a42f95d3f259f18b5f211dd112d03df9f78dd (diff) | |
mb/google/hatch: Enable console UART
This patch incorporates following changes to enable console on UART0
1. update default console number to 0
2. Enable PCI port for UART0
GPIO configuration will be done by coreboot based on correct console
number.
Change-Id: I735d33674b276b28e2cbb753d3a6d83edbabe89d
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'src/mainboard/google/hatch/variants/baseboard/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 164c842485..0b3f469b77 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -85,7 +85,7 @@ chip soc/intel/cannonlake device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 off end # PCI Express Port 13 (x4) - device pci 1e.0 off end # UART #0 + device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 on chip drivers/spi/acpi |