diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2018-12-18 16:09:27 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-12-21 04:42:33 +0000 |
| commit | 6d8e0cdeabf0b0a128d9863a6f190facc73f4880 (patch) | |
| tree | 1d84b73b4a0e1a6852ca4f3f964bfe37aaed52dd /src/mainboard/google/hatch/variants/baseboard/devicetree.cb | |
| parent | 368598198d5c741d64b38d358e84c1694f97f486 (diff) | |
mb/google/hatch: Enable H1 TPM support over SPI interface
Add code support to enable H1 TPM interfaced to SOC on GSPI0.
The TPM interrupt is mapped to GPP_C21.
BUG=b:120914069
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot
Change-Id: Ib63a0b473f632d91745102ebd01993e8d65b9552
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30210
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/hatch/variants/baseboard/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 36 |
1 files changed, 35 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 88df092155..4fe0c4cd70 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -1,4 +1,31 @@ chip soc/intel/cannonlake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # DW1 is used by: + # - GPP_C21 - H1_PCH_INT_ODL + register "gpe0_dw0" = "PMC_GPP_A" + register "gpe0_dw1" = "PMC_GPP_C" + register "gpe0_dw2" = "PMC_GPP_D" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + }" + device domain 0 on device pci 00.0 off end # Host Bridge device pci 02.0 off end # Integrated Graphics Device @@ -39,7 +66,14 @@ chip soc/intel/cannonlake device pci 1d.4 off end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 + device pci 1e.2 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)" + device spi 0 on end + end + end # GSPI #0 device pci 1e.3 off end # GSPI #1 device pci 1f.0 off end # LPC/eSPI device pci 1f.1 off end # P2SB |