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authorPhilip Chen <philipchen@google.com>2019-04-05 15:26:13 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-04-09 17:23:33 +0000
commit61d365fafdb2100aabf4d39bf525e5364d1db5e8 (patch)
tree7280efc1d816d65c1555a8c167cca28735e0ba06 /src/mainboard/google/hatch/chromeos-16MiB.fmd
parent15589b4e56081b5d15e8c8f3c0e5185d62573299 (diff)
mb/google/hatch: Support 16MiB fmap
Add a fmd file for 16MiB fmap, so that we can support both 16MiB / 32MiB SPI flash ROM chips. BUG=b:129464811 TEST=build hatch firmware image with 16MiB fmap and verify fmap is updated by 'fuility dump_fmap' Change-Id: Ifc0103c7fd0d99439f40a31d23422401a6dce826 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/hatch/chromeos-16MiB.fmd')
-rw-r--r--src/mainboard/google/hatch/chromeos-16MiB.fmd42
1 files changed, 42 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/chromeos-16MiB.fmd b/src/mainboard/google/hatch/chromeos-16MiB.fmd
new file mode 100644
index 0000000000..1594ab3a52
--- /dev/null
+++ b/src/mainboard/google/hatch/chromeos-16MiB.fmd
@@ -0,0 +1,42 @@
+FLASH@0xff000000 0x1000000 {
+ SI_ALL@0x0 0x400000 {
+ SI_DESC@0x0 0x1000
+ SI_ME@0x1000 0x3ff000
+ }
+ SI_BIOS@0x400000 0xc00000 {
+ RW_SECTION_A@0x0 0x380000 {
+ VBLOCK_A@0x0 0x10000
+ FW_MAIN_A(CBFS)@0x10000 0x36ffc0
+ RW_FWID_A@0x37ffc0 0x40
+ }
+ RW_SECTION_B@0x380000 0x380000 {
+ VBLOCK_B@0x0 0x10000
+ FW_MAIN_B(CBFS)@0x10000 0x36ffc0
+ RW_FWID_B@0x37ffc0 0x40
+ }
+ RW_MISC@0x700000 0x30000 {
+ UNIFIED_MRC_CACHE@0x0 0x20000 {
+ RECOVERY_MRC_CACHE@0x0 0x10000
+ RW_MRC_CACHE@0x10000 0x10000
+ }
+ RW_ELOG(PRESERVE)@0x20000 0x4000
+ RW_SHARED@0x24000 0x4000 {
+ SHARED_DATA@0x0 0x2000
+ VBLOCK_DEV@0x2000 0x2000
+ }
+ RW_VPD(PRESERVE)@0x28000 0x2000
+ RW_NVRAM(PRESERVE)@0x2a000 0x6000
+ }
+ RW_LEGACY(CBFS)@0x730000 0xd0000
+ WP_RO@0x800000 0x400000 {
+ RO_VPD(PRESERVE)@0x0 0x4000
+ RO_SECTION@0x4000 0x3fc000 {
+ FMAP@0x0 0x800
+ RO_FRID@0x800 0x40
+ RO_FRID_PAD@0x840 0x7c0
+ GBB@0x1000 0xef000
+ COREBOOT(CBFS)@0xf0000 0x30c000
+ }
+ }
+ }
+}