diff options
| author | Robert Zieba <robertzieba@google.com> | 2022-01-19 14:15:24 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-23 19:37:36 +0000 |
| commit | e2bde83a518d10fc6eaa7edca507daf271fdcf0a (patch) | |
| tree | 3321d68cbeff8d57ee3c5b20888e0cc5b27e28bf /src/mainboard/google/guybrush | |
| parent | e58de0db450027f2f71c468d71b91d0b297a758f (diff) | |
soc/amd/cezanne: Turn off gpp clock request for disabled devices
The current behavior does not actually check if a device is present
before enabling the corresponding gpp_clkx_clock_request_mapping bits
which may cause issues with L1SS. This change sets the corresponding
gpp_clkx_clock_request_mapping to off if the corresponding device is
disabled.
BUG=b:202252869
TEST=Checked that value of GPP_CLK_CNTRL matched the expected value
when devices are enabled/disabled, checked that physically removing a
device that is marked as enabled also disables the corresponding clk req
BRANCH=guybrush
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61259
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/guybrush')
| -rw-r--r-- | src/mainboard/google/guybrush/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/Makefile.inc b/src/mainboard/google/guybrush/Makefile.inc index cdfb53bd63..1158dcfaca 100644 --- a/src/mainboard/google/guybrush/Makefile.inc +++ b/src/mainboard/google/guybrush/Makefile.inc @@ -8,6 +8,7 @@ romstage-y += romstage.c ramstage-y += mainboard.c ramstage-y += ec.c +ramstage-y += port_descriptors.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c all-y += spi_speeds.c |