diff options
| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2021-10-08 17:04:10 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-14 13:10:17 +0000 |
| commit | d086e3d6e42036b1ec0fc2173db5386279ac838b (patch) | |
| tree | 6ce0defd0eb24c53830f98fbf00d8ed895499967 /src/mainboard/google/guybrush | |
| parent | e7f43502b540a42f23a967b6206370050ef75f23 (diff) | |
mb/google/guybrush: Assert WWAN_AUX_RST_L on S0i3 entry
Currently WWAN_AUX_RST_L is in S5 domain and does not get asserted on
S0i3 entry. Based on the schematics, the pull-down on that signal leads
to 10 mW power leakage on S0i3 entry. Assert the signal on S0i3 entry to
achieve some power savings and de-assert it on S0i3 exit.
BUG=b:195748540
TEST=Build and boot to OS in Guybrush. Ensure that the signal gets
asserted on S0i3 entry and de-asserted on S0i3 exit. Trigger
suspend/resume cycles and ensure that the WWAN module is enumerated
after each cycle.
Change-Id: I43c8655ee5209779748e4365db973e094cb08aca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58275
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/guybrush')
| -rw-r--r-- | src/mainboard/google/guybrush/mainboard.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c index 3626157338..39ef2a0795 100644 --- a/src/mainboard/google/guybrush/mainboard.c +++ b/src/mainboard/google/guybrush/mainboard.c @@ -13,11 +13,13 @@ #include <vendorcode/google/chromeos/chromeos.h> #define BACKLIGHT_GPIO GPIO_129 +#define WWAN_AUX_RST_GPIO GPIO_18 #define METHOD_BACKLIGHT_ENABLE "\\_SB.BKEN" #define METHOD_BACKLIGHT_DISABLE "\\_SB.BKDS" #define METHOD_MAINBOARD_INI "\\_SB.MINI" #define METHOD_MAINBOARD_WAK "\\_SB.MWAK" #define METHOD_MAINBOARD_PTS "\\_SB.MPTS" +#define METHOD_MAINBOARD_S0X "\\_SB.MS0X" /* * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -151,6 +153,31 @@ static void mainboard_write_mpts(void) acpigen_pop_len(); } +static void mainboard_assert_wwan_aux_reset(void) +{ + if (variant_has_pcie_wwan()) + acpigen_soc_clear_tx_gpio(WWAN_AUX_RST_GPIO); +} + +static void mainboard_deassert_wwan_aux_reset(void) +{ + if (variant_has_pcie_wwan()) + acpigen_soc_set_tx_gpio(WWAN_AUX_RST_GPIO); +} + +static void mainboard_write_ms0x(void) +{ + acpigen_write_method_serialized(METHOD_MAINBOARD_S0X, 1); + /* S0ix Entry */ + acpigen_write_if_lequal_op_int(ARG0_OP, 1); + mainboard_assert_wwan_aux_reset(); + /* S0ix Exit */ + acpigen_write_else(); + mainboard_deassert_wwan_aux_reset(); + acpigen_pop_len(); + acpigen_pop_len(); +} + static void mainboard_fill_ssdt(const struct device *dev) { mainboard_write_blken(); @@ -158,6 +185,7 @@ static void mainboard_fill_ssdt(const struct device *dev) mainboard_write_mini(); mainboard_write_mpts(); mainboard_write_mwak(); + mainboard_write_ms0x(); } static void mainboard_enable(struct device *dev) |