mb/google/guybrush: Rename pcie_gpio_table to romstage_gpio_table

Rename so table more indicative of when GPIOs are set, and so it can
be used for more than just setting PCIe GPIOs. Will be used to set
touchscreen GPIOs as part of power sequencing in a subsequent commit.

Rename all variant tables and getter functions to match.

This mirrors the changes made for skyrim in CB:67810

Change-Id: I72e7febfb532262be7e4c14bf136e0d69c91301e
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

6 files changed, 22 insertions, 22 deletions

diff --git a/src/mainboard/google/guybrush/romstage.c b/src/mainboard/google/guybrush/romstage.c
index 0b7649b87a..571eb449f3 100644
--- a/src/mainboard/google/guybrush/romstage.c
+++ b/src/mainboard/google/guybrush/romstage.c
@@ -8,9 +8,9 @@ void mb_pre_fspm(void)
 	size_t base_num_gpios, override_num_gpios;
 	const struct soc_amd_gpio *base_gpios, *override_gpios;
 
-	/* Initialize PCIe reset. */
-	base_gpios = baseboard_pcie_gpio_table(&base_num_gpios);
-	override_gpios = variant_pcie_override_gpio_table(&override_num_gpios);
+	/* Initialize PCIe reset and other romstage GPIOs */
+	base_gpios = baseboard_romstage_gpio_table(&base_num_gpios);
+	override_gpios = variant_romstage_override_gpio_table(&override_num_gpios);
 
 	gpio_configure_pads_with_override(base_gpios, base_num_gpios,
 			override_gpios, override_num_gpios);
diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
index 1ee70dae33..beb654f013 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c
+++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
@@ -268,7 +268,7 @@ static const struct soc_amd_gpio bootblock_gpio_table[] = {
 };
 
 /* PCIE_RST needs to be brought high before FSP-M runs */
-static const struct soc_amd_gpio pcie_gpio_table[] = {
+static const struct soc_amd_gpio romstage_gpio_table[] = {
 	/* Deassert all AUX_RESET lines & PCIE_RST */
 	/* Unused */
 	PAD_NC(GPIO_5),
@@ -286,10 +286,10 @@ static const struct soc_amd_gpio pcie_gpio_table[] = {
 	PAD_NFO(GPIO_26, PCIE_RST_L, HIGH),
 };
 
-const struct soc_amd_gpio *baseboard_pcie_gpio_table(size_t *size)
+const struct soc_amd_gpio *baseboard_romstage_gpio_table(size_t *size)
 {
-	*size = ARRAY_SIZE(pcie_gpio_table);
-	return pcie_gpio_table;
+	*size = ARRAY_SIZE(romstage_gpio_table);
+	return romstage_gpio_table;
 }
 
 const struct soc_amd_gpio *__weak variant_bootblock_gpio_table(size_t *size)
@@ -322,7 +322,7 @@ const struct soc_amd_gpio * __weak variant_bootblock_override_gpio_table(size_t
 	return NULL;
 }
 
-const struct soc_amd_gpio * __weak variant_pcie_override_gpio_table(size_t *size)
+const struct soc_amd_gpio * __weak variant_romstage_override_gpio_table(size_t *size)
 {
 	*size = 0;
 	return NULL;
diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
index 9a57c41eff..24c03b0cb3 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
@@ -21,7 +21,7 @@ const struct soc_amd_gpio *baseboard_gpio_table(size_t *size);
 const struct soc_amd_gpio *variant_override_gpio_table(size_t *size);
 const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size);
 const struct soc_amd_gpio *variant_bootblock_override_gpio_table(size_t *size);
-const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size);
+const struct soc_amd_gpio *variant_romstage_override_gpio_table(size_t *size);
 
 /* This function provides early GPIO init in early bootblock or psp. */
 const struct soc_amd_gpio *variant_early_gpio_table(size_t *size);
@@ -30,7 +30,7 @@ const struct soc_amd_gpio *variant_early_gpio_table(size_t *size);
 const struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size);
 
 /* This function provides GPIO settings before PCIe enumeration. */
-const struct soc_amd_gpio *baseboard_pcie_gpio_table(size_t *size);
+const struct soc_amd_gpio *baseboard_romstage_gpio_table(size_t *size);
 
 /* This function provides GPIO settings for eSPI bus. */
 const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size);
diff --git a/src/mainboard/google/guybrush/variants/dewatt/gpio.c b/src/mainboard/google/guybrush/variants/dewatt/gpio.c
index 10486351a9..571cbb4632 100644
--- a/src/mainboard/google/guybrush/variants/dewatt/gpio.c
+++ b/src/mainboard/google/guybrush/variants/dewatt/gpio.c
@@ -53,7 +53,7 @@ static const struct soc_amd_gpio override_early_gpio_table[] = {
 };
 
 /* This table is used by guybrush variant */
-static const struct soc_amd_gpio override_pcie_gpio_table[] = {
+static const struct soc_amd_gpio override_romstage_gpio_table[] = {
 	/* Unused TP195*/
 	PAD_NC(GPIO_18),
 	/* Unused TP217*/
@@ -78,10 +78,10 @@ const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size)
 	return override_early_gpio_table;
 }
 
-const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size)
+const struct soc_amd_gpio *variant_romstage_override_gpio_table(size_t *size)
 {
-	*size = ARRAY_SIZE(override_pcie_gpio_table);
-	return override_pcie_gpio_table;
+	*size = ARRAY_SIZE(override_romstage_gpio_table);
+	return override_romstage_gpio_table;
 }
 
 const struct soc_amd_gpio *variant_bootblock_override_gpio_table(size_t *size)
diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c
index f3ed09fa29..dcbda20f7f 100644
--- a/src/mainboard/google/guybrush/variants/guybrush/gpio.c
+++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c
@@ -48,7 +48,7 @@ static const struct soc_amd_gpio override_early_gpio_table[] = {
 };
 
 /* This table is used by guybrush variant with board version < 2. */
-static const struct soc_amd_gpio bid1_pcie_gpio_table[] = {
+static const struct soc_amd_gpio bid1_romstage_gpio_table[] = {
 	/* SD_AUX_RESET_L */
 	PAD_GPO(GPIO_70, HIGH),
 };
@@ -87,13 +87,13 @@ const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size)
 	return override_early_gpio_table;
 }
 
-const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size)
+const struct soc_amd_gpio *variant_romstage_override_gpio_table(size_t *size)
 {
 	uint32_t board_version = board_id();
 	*size = 0;
 	if (board_version < 2) {
-		*size = ARRAY_SIZE(bid1_pcie_gpio_table);
-		return bid1_pcie_gpio_table;
+		*size = ARRAY_SIZE(bid1_romstage_gpio_table);
+		return bid1_romstage_gpio_table;
 	}
 
 	return NULL;
diff --git a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c
index 0fdedbf8dd..c9f637c739 100644
--- a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c
+++ b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c
@@ -47,7 +47,7 @@ static const struct soc_amd_gpio override_early_gpio_table[] = {
 	PAD_GPO(GPIO_31, LOW),
 };
 
-static const struct soc_amd_gpio override_pcie_gpio_table[] = {
+static const struct soc_amd_gpio override_romstage_gpio_table[] = {
 	PAD_NC(GPIO_18),
 };
 
@@ -91,10 +91,10 @@ const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size)
 	return override_early_gpio_table;
 }
 
-const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size)
+const struct soc_amd_gpio *variant_romstage_override_gpio_table(size_t *size)
 {
-	*size = ARRAY_SIZE(override_pcie_gpio_table);
-	return override_pcie_gpio_table;
+	*size = ARRAY_SIZE(override_romstage_gpio_table);
+	return override_romstage_gpio_table;
 }
 
 const struct soc_amd_gpio *variant_tpm_gpio_table(size_t *size)