diff options
| author | Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> | 2021-10-27 16:42:16 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-11-02 08:21:51 +0000 |
| commit | c47835d5990d9d669b57a684fd8f34f322e5d70c (patch) | |
| tree | 3e4c7f4120a3a0fcab64d29501959451213c33e7 /src/mainboard/google/guybrush/variants | |
| parent | dd30f4b112da8ee8dd84aef1734c97ae5c84e32c (diff) | |
mb/google/guybrush: Update STT coefficients
Update guybrush STT (Skin Temperature Tracking) configuration settings
to values provided by power team after tuning.
BUG=b:203123658
Change-Id: I14c69dbe044e4f3f2711be96e5ea80db0686b3eb
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Diffstat (limited to 'src/mainboard/google/guybrush/variants')
| -rw-r--r-- | src/mainboard/google/guybrush/variants/baseboard/devicetree.cb | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 8a9543da2b..7fb3c7e6c8 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -52,23 +52,23 @@ chip soc/amd/cezanne register "stt_control" = "1" register "stt_pcb_sensor_count" = "2" register "stt_min_limit" = "0" - register "stt_m1" = "0x0319" - register "stt_m2" = "0x01A0" + register "stt_m1" = "0x03A0" + register "stt_m2" = "0xFFC9" register "stt_m3" = "0" register "stt_m4" = "0" register "stt_m5" = "0" register "stt_m6" = "0" - register "stt_c_apu" = "0xE99F" + register "stt_c_apu" = "0x0901" register "stt_c_gpu" = "0" register "stt_c_hs2" = "0" - register "stt_alpha_apu" = "0xCCD" + register "stt_alpha_apu" = "0x199A" register "stt_alpha_gpu" = "0" register "stt_alpha_hs2" = "0" register "stt_skin_temp_apu" = "0x2D00" register "stt_skin_temp_gpu" = "0" register "stt_skin_temp_hs2" = "0" - register "stt_error_coeff" = "0xD" - register "stt_error_rate_coefficient" = "0x8F6" + register "stt_error_coeff" = "0x21" + register "stt_error_rate_coefficient" = "0xCCD" register "system_configuration" = "2" |