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authorJulian Schroeder <julianmarcusschroeder@gmail.com>2021-09-07 14:54:19 -0500
committerFelix Held <felix-coreboot@felixheld.de>2021-09-08 20:45:33 +0000
commit46719834010ce1f4c8ecbc12c9c52baa349ecf9d (patch)
treee7b1fcf3c593674936dd3660eef8baf7961288e6 /src/mainboard/google/guybrush/variants
parentf4a992cca73f227ac86a4e9590198cea72b8b767 (diff)
soc/amd/cezanne/fsp_m_params: set usb_phy version and length.
Setting the usb_phy version and length in the soc code instead of devicetree. That way the devicetree code does not have to reapeat it for different AMD Cezanne based systems. Tested on guybrush by changing phy settings in devicetree and then checking the usb phy register. Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: I2db49e095672054b9b15042fb003a93b67e3a4c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/google/guybrush/variants')
-rw-r--r--src/mainboard/google/guybrush/variants/baseboard/devicetree.cb4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
index be7b5aea15..8629a64036 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
@@ -206,12 +206,8 @@ chip soc/amd/cezanne
.tx_vboost_lvl_en=1,
.tx_vboost_lvl=5,
},
-
.ComboPhyStaticConfig[0] = 0,
.ComboPhyStaticConfig[1] = 0,
- .Version_Major = 0xd,
- .Version_Minor = 0x6,
- .TableLength = 100,
.BatteryChargerEnable = 0,
.PhyP3CpmP4Support = 0,
}"