mb/google/guybrush: Move GSC_SOC_INT_L from GPIO_3 to GPIO_85

GSC_SOC_INT_L gpio is used by Google Security Chip (GSC) to interrupt
SoC when the SoC is in S0 state. Hence use GPIO_85 which is in S0 domain
and save the GPIO_3 in S5 domain for other use-cases. This move applies
to all board except:
* Guybrush
* Nipperkin board version 1

Update the GPIO configuration, device tree configuration accordingly.

BUG=b:202992077
TEST=Build and boot to OS in Guybrush and Nipperkin. Ensure that the SoC
<-> TPM communication is working fine.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I019f10f2f457ab81bcff77ce8ca609b2b40cb2ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

1 files changed, 5 insertions, 0 deletions

diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c
index 39ef2a0795..b2d669c443 100644
--- a/src/mainboard/google/guybrush/mainboard.c
+++ b/src/mainboard/google/guybrush/mainboard.c
@@ -112,10 +112,15 @@ static void mainboard_configure_gpios(void)
 					  override_num_gpios);
 }
 
+void __weak variant_devtree_update(void)
+{
+}
+
 static void mainboard_init(void *chip_info)
 {
 	mainboard_configure_gpios();
 	mainboard_ec_init();
+	variant_devtree_update();
 }
 
 static void mainboard_write_blken(void)