diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-01-10 23:37:58 +0100 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-01-14 00:29:52 +0000 |
| commit | 62afdb675a49bfebbdd4f186f696c15a56d64348 (patch) | |
| tree | 50fa03f35315cb3e6e13c3960bd1b6d5c0aae288 /src/mainboard/google/guybrush/bootblock.c | |
| parent | 45b6080561748fe579c8ee901811cf4043383c2f (diff) | |
soc/amd/cezanne: factor out eSPI SPI2 pads configuration functions
verstage_mainboard_espi_init in mb/guybrush/verstage.c still accesses
some of the registers directly.
BUG=b:183149183
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2f48d1c62b48866d8d942f1586bcb72017b8dd72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/mainboard/google/guybrush/bootblock.c')
| -rw-r--r-- | src/mainboard/google/guybrush/bootblock.c | 24 |
1 files changed, 3 insertions, 21 deletions
diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index 2791a8ff6f..800e70a294 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -1,15 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <amdblocks/acpimmio.h> #include <amdblocks/espi.h> -#include <amdblocks/lpc.h> #include <bootblock_common.h> #include <baseboard/variants.h> #include <console/console.h> #include <delay.h> -#include <device/pci_ops.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> +#include <soc/espi.h> #include <soc/southbridge.h> #include <timer.h> @@ -30,16 +26,10 @@ void mb_set_up_early_espi(void) void bootblock_mainboard_early_init(void) { - uint32_t dword; size_t num_gpios, override_num_gpios; const struct soc_amd_gpio *gpios, *override_gpios; - /* Beware that the bit definitions for LPC_LDRQ0_PU_EN and LPC_LDRQ0_PD_EN are swapped - on Picasso and older compared to Renoir/Cezanne and newer */ - dword = pci_read_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS); - dword &= ~(LPC_LDRQ0_PU_EN | LPC_LDRQ1_EN | LPC_LDRQ0_EN); - dword |= LPC_LDRQ0_PD_EN; - pci_write_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS, dword); + espi_disable_lpc_ldrq(); /* * All LPC decodes need to be cleared before we can configure the LPC pads as secondary @@ -67,15 +57,7 @@ void bootblock_mainboard_early_init(void) /* Early eSPI interface configuration */ - /* Use SPI2 pins for eSPI */ - dword = pm_read32(PM_SPI_PAD_PU_PD); - dword |= PM_ESPI_CS_USE_DATA2; - pm_write32(PM_SPI_PAD_PU_PD, dword); - - /* Switch the pads that can be used as either LPC or secondary eSPI to 1.8V mode */ - dword = pm_read32(PM_ACPI_CONF); - dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; - pm_write32(PM_ACPI_CONF, dword); + espi_switch_to_spi2_pads(); } void bootblock_mainboard_init(void) |