diff options
| author | Matt Papageorge <matthewpapa07@gmail.com> | 2021-03-30 11:41:22 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-04-07 22:49:08 +0000 |
| commit | ea0f225249221edc75640756889f9e67992c4b90 (patch) | |
| tree | 9ceb5dd9fc4473951b0f66c63d89eed28c19398c /src/mainboard/google/guybrush/Makefile.inc | |
| parent | 2789952302b0d9df909f89c7caf48ee1a5a4f784 (diff) | |
soc/amd/cezanne: Pass DXIO and DDI Descriptors to FSP
This patch adds the functionality to write the DXIO and DDI descriptors
to the UPD data structure to the SoC code and adds the
mainboard_get_dxio_ddi_descriptors function to each mainboard using the
Cezanne SoC that gets called to get the descriptors from the board code.
Change-Id: I1cb36addcf0202cd56ce99e610a13d6d230bc981
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/mainboard/google/guybrush/Makefile.inc')
| -rw-r--r-- | src/mainboard/google/guybrush/Makefile.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/Makefile.inc b/src/mainboard/google/guybrush/Makefile.inc index 263483fd33..d4eeaf5e56 100644 --- a/src/mainboard/google/guybrush/Makefile.inc +++ b/src/mainboard/google/guybrush/Makefile.inc @@ -10,6 +10,8 @@ else $(info APCB sources not found. Skipping APCB.) endif +romstage-y += port_descriptors.c + ramstage-y += mainboard.c ramstage-y += ec.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c |