diff options
| author | Lin Huang <hl@rock-chips.com> | 2016-09-15 22:59:55 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-11-02 17:29:48 +0100 |
| commit | 883f5cbdcea6e8e4dbca57ff0a430338c9159ed2 (patch) | |
| tree | 5fb86a9b3dcc8537c240c81ebafd275897fe9948 /src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c | |
| parent | 84164603188175abd2a3d8eeab1adc5efc33330f (diff) | |
rockchip/rk3399: sdram: also prepare the index1 configuration
To enable DDR Dynamic Voltage and Frequency Scaling (DVFS) we need to
train alternative configurations first, so do the training and store the
values.
BUG=None
BRANCH=None
TEST=Boot from kevin
Change-Id: I944a4b297a4ed6966893aa09553da88171307a42
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 94533ff3ba21bcb0ace00bedcf0cebb89a341be2
Original-Change-Id: I4a98bc0db5553d154fedb657e35b926a92aa80c7
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/386596
Original-Commit-Ready: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17104
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c')
| -rw-r--r-- | src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c index 3947881856..7110748940 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c @@ -201,7 +201,7 @@ struct rk3399_sdram_params params = { 0x0000001c, /* DENALI_CTL_137_DATA */ 0x00010001, /* DENALI_CTL_138_DATA */ 0x06000001, /* DENALI_CTL_139_DATA */ - 0x00000707, /* DENALI_CTL_140_DATA */ + 0x00000606, /* DENALI_CTL_140_DATA */ 0x00000000, /* DENALI_CTL_141_DATA */ 0x00000000, /* DENALI_CTL_142_DATA */ 0x00000000, /* DENALI_CTL_143_DATA */ @@ -215,7 +215,7 @@ struct rk3399_sdram_params params = { 0x0000001c, /* DENALI_CTL_151_DATA */ 0x00010001, /* DENALI_CTL_152_DATA */ 0x06000001, /* DENALI_CTL_153_DATA */ - 0x00000707, /* DENALI_CTL_154_DATA */ + 0x00000606, /* DENALI_CTL_154_DATA */ 0x00000000, /* DENALI_CTL_155_DATA */ 0x00000000, /* DENALI_CTL_156_DATA */ 0x00000000, /* DENALI_CTL_157_DATA */ @@ -278,7 +278,7 @@ struct rk3399_sdram_params params = { 0x04040001, /* DENALI_CTL_214_DATA */ 0x0c0c0c04, /* DENALI_CTL_215_DATA */ 0x08080808, /* DENALI_CTL_216_DATA */ - 0x02050103, /* DENALI_CTL_217_DATA */ + 0x08050103, /* DENALI_CTL_217_DATA */ 0x02050103, /* DENALI_CTL_218_DATA */ 0x00050103, /* DENALI_CTL_219_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */ |