rockchip/rk3399: Add pwm_regulator.c for pwm then ramp boot up cpu

Before, we calculate the pwm duties for cpu cores and centerlogic by
hand, adding pwm_regulator.c to handle this. The default pwm design
min/max voltage may be different between revs.

With the pwm regulator, this patch changes the little cpu frequency from
600M to 1512M, and raises CPU voltage to 1.2V correspondingly.

This also means we decide to drop the ES1 because it may fail to
bootup with 1.5G ~ 1.2v.

BRANCH=none
BUG=chrome-os-partner:54376,chrome-os-partner:54862
TEST=Bootup on kevin board

Change-Id: Id04c176bddfb9cdf3d25b65736e40249a85f6aa1
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: ee4365c787ec523b7ee1028ea100dcfbb331b3a9
Original-Change-Id: Ide75bbd92d1cbb14f934baeec0e38862bc08402b
Original-Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/364410
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16368
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 5 insertions, 67 deletions

diff --git a/src/mainboard/google/gru/romstage.c b/src/mainboard/google/gru/romstage.c
index ccf42b9b5f..1e2507a29e 100644
--- a/src/mainboard/google/gru/romstage.c
+++ b/src/mainboard/google/gru/romstage.c
@@ -17,90 +17,28 @@
 #include <arch/cache.h>
 #include <arch/cpu.h>
 #include <arch/exception.h>
-#include <arch/io.h>
 #include <arch/mmu.h>
-#include <boardid.h>
 #include <cbfs.h>
 #include <console/console.h>
-#include <delay.h>
 #include <program_loading.h>
 #include <romstage_handoff.h>
 #include <soc/addressmap.h>
-#include <soc/grf.h>
 #include <soc/mmu_operations.h>
-#include <soc/pwm.h>
 #include <soc/tsadc.h>
 #include <soc/sdram.h>
 #include <symbols.h>
 #include <soc/usb.h>
 
+#include "pwm_regulator.h"
+
 static const uint64_t dram_size =
 	(uint64_t)min((uint64_t)CONFIG_DRAM_SIZE_MB * MiB, MAX_DRAM_ADDRESS);
 
 static void init_dvs_outputs(void)
 {
-	int duty_ns;
-	uint32_t i;
-	uint32_t id;
-
-	write32(&rk3399_grf->iomux_pwm_0, IOMUX_PWM_0);		/* GPU */
-	write32(&rk3399_grf->iomux_pwm_1, IOMUX_PWM_1);		/* Big */
-	write32(&rk3399_pmugrf->iomux_pwm_2, IOMUX_PWM_2);	/* Little */
-	write32(&rk3399_pmugrf->iomux_pwm_3a, IOMUX_PWM_3_A);	/* Centerlog */
-
-	/*
-	 * Set up voltages for all DVS rails.
-	 *
-	 * LITTLE CPU: At the speed we're running at right now and on the
-	 * early silicon, .9V is sane.  If/when we run faster, let's bump this.
-	 *
-	 * CENTER LOGIC: There are some claims that this should simply always
-	 * be .9 V.  There are other claims that say that we need to adjust this
-	 * dynamically depending on the memory frequency.  Until this is sorted
-	 * out, it appears that .9 V works for the 800 MHz.
-	 *
-	 * BIG CPU / GPU: These aren't used in coreboot.  Init to .9V which is
-	 * supposed to be a good default.
-	 *
-	 * Details:
-	 *   design_min = 0.8
-	 *   design_max = 1.5
-	 *   period = 3337     # 300 kHz
-	 *   volt = 1.1
-	 *   # Intentionally round down (higher volt) to be safe.
-	 *   int((period / (design_max - design_min)) * (design_max - volt))
-	 *
-	 * Apparently a period of 3333 is determined by EEs to be ideal for our
-	 * board design / resistors / capacitors / regulators but due to
-	 * clock dividers we actually get 3337.  Solving, we get:
-	 *   period = 3337, volt = 1.1: 1906
-	 *   period = 3337, volt = 1.0: 2383
-	 *   period = 3337, volt = 0.9: 2860
-	 */
-	duty_ns = 2860; /* 0.9v */
-
-	/* TODO: Clean all this up, implement proper pwm_regulator driver. */
-	if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) {
-		id = board_id();
-		if (id <= 2)
-			duty_ns = 1906; /* 1.1v */
-		else if (id == 3)
-			duty_ns = 2621; /* 0.95v */
-		else if (id >= 6) {
-			/* GPU: 3337 * (12043 - 9000) / (12043 - 7984) = 2501 */
-			pwm_init(0, 3337, 2501);
-			/* BIG: 3337 * (12837 - 9000) / (12837 - 7985) = 2638 */
-			pwm_init(1, 3337, 2638);
-			/* LIT: 3337 * (12807 - 9000) / (12807 - 8009) = 2647 */
-			pwm_init(2, 3337, 2647);
-			/* CTR: 3337 * (10507 - 9500) / (10507 - 7996) = 1338 */
-			pwm_init(3, 3337, 1338);
-			return;
-		}
-	}
-
-	for (i = 0; i < 4; i++)
-		pwm_init(i, 3337, duty_ns);
+	pwm_regulator_configure(PWM_REGULATOR_GPU, 900);
+	pwm_regulator_configure(PWM_REGULATOR_BIG, 900);
+	pwm_regulator_configure(PWM_REGULATOR_CENTERLOG, 950);
 }
 
 static void prepare_usb(void)