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authorLin Huang <hl@rock-chips.com>2017-11-22 09:40:50 +0800
committerJulius Werner <jwerner@chromium.org>2017-11-28 19:16:09 +0000
commit25fb09b0684769bd010cde0aa60f1b32eddb2cba (patch)
treedb7ef455bfcb34369603f6513e3eeb8c8b8cd2c4 /src/mainboard/google/gru/devicetree.scarlet.cb
parent45f1b01324ed1712092e80fed7e03fe088452729 (diff)
rockchip/rk3399: support dual mipi dsi
Refactor the mipi driver, so we can support dual mipi panel. And pass the panel data from mainboard.c, that we can support different panel with different board. Change-Id: Id1286c0ccbe50c89514c8daee66439116d3f1ca4 Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/mainboard/google/gru/devicetree.scarlet.cb')
-rw-r--r--src/mainboard/google/gru/devicetree.scarlet.cb12
1 files changed, 0 insertions, 12 deletions
diff --git a/src/mainboard/google/gru/devicetree.scarlet.cb b/src/mainboard/google/gru/devicetree.scarlet.cb
index f1129a4980..c4417c594c 100644
--- a/src/mainboard/google/gru/devicetree.scarlet.cb
+++ b/src/mainboard/google/gru/devicetree.scarlet.cb
@@ -17,16 +17,4 @@ chip soc/rockchip/rk3399
device cpu_cluster 0 on end
register "vop_mode" = "VOP_MODE_MIPI"
register "framebuffer_bits_per_pixel" = "32"
- register "panel_pixel_clock" = "56900"
- register "panel_refresh" = "60"
- register "panel_ha" = "768"
- register "panel_hbl" = "120"
- register "panel_hso" = "40"
- register "panel_hspw" = "40"
- register "panel_va" = "1024"
- register "panel_vbl" = "44"
- register "panel_vso" = "20"
- register "panel_vspw" = "4"
- register "panel_display_on_mdelay" = "120"
- register "panel_video_mode_mdelay" = "5"
end