summaryrefslogtreecommitdiff
path: root/src/mainboard/google/glados
diff options
context:
space:
mode:
authorSumeet R Pawnikar <sumeet.r.pawnikar@intel.com>2020-05-10 01:24:11 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-05-18 07:13:23 +0000
commit97c5464443306f26b61cec3a0f50108a5c06b7ef (patch)
treef085457907ad200a0d9d9be8a07c937e755fae91 /src/mainboard/google/glados
parent19c2ce7639d55908d210782ae5a0315396cc7eaf (diff)
skylake: update processor power limits configuration
Update processor power limit configuration parameters based on common code base support for Intel Skylake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on nami system Change-Id: Idc82f3d2f805b92fb3005d2f49098e55cb142e45 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/glados')
-rw-r--r--src/mainboard/google/glados/devicetree.cb4
-rw-r--r--src/mainboard/google/glados/variants/caroline/overridetree.cb4
-rw-r--r--src/mainboard/google/glados/variants/cave/overridetree.cb4
-rw-r--r--src/mainboard/google/glados/variants/chell/overridetree.cb4
-rw-r--r--src/mainboard/google/glados/variants/glados/overridetree.cb4
5 files changed, 15 insertions, 5 deletions
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 4e85e21111..f7be80d460 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -99,7 +99,9 @@ chip soc/intel/skylake
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
# PL2 override 25W
- register "tdp_pl2_override" = "25"
+ register "power_limits_config" = "{
+ .tdp_pl2_override = 25,
+ }"
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
diff --git a/src/mainboard/google/glados/variants/caroline/overridetree.cb b/src/mainboard/google/glados/variants/caroline/overridetree.cb
index ce364801ca..7bee2e2a48 100644
--- a/src/mainboard/google/glados/variants/caroline/overridetree.cb
+++ b/src/mainboard/google/glados/variants/caroline/overridetree.cb
@@ -25,7 +25,9 @@ chip soc/intel/skylake
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
# PL2 override 15W
- register "tdp_pl2_override" = "15"
+ register "power_limits_config" = "{
+ .tdp_pl2_override = 15,
+ }"
# Send an extra VR mailbox command for the supported MPS IMVP8 model
register "SendVrMbxCmd" = "1"
diff --git a/src/mainboard/google/glados/variants/cave/overridetree.cb b/src/mainboard/google/glados/variants/cave/overridetree.cb
index ae32b3dabf..9aeb78afa7 100644
--- a/src/mainboard/google/glados/variants/cave/overridetree.cb
+++ b/src/mainboard/google/glados/variants/cave/overridetree.cb
@@ -18,7 +18,9 @@ chip soc/intel/skylake
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A Port 2
# PL2 override 15W
- register "tdp_pl2_override" = "15"
+ register "power_limits_config" = "{
+ .tdp_pl2_override = 15,
+ }"
# Send an extra VR mailbox command for the supported MPS IMVP8 model
register "SendVrMbxCmd" = "1"
diff --git a/src/mainboard/google/glados/variants/chell/overridetree.cb b/src/mainboard/google/glados/variants/chell/overridetree.cb
index c6ccd208aa..ad3ae391c7 100644
--- a/src/mainboard/google/glados/variants/chell/overridetree.cb
+++ b/src/mainboard/google/glados/variants/chell/overridetree.cb
@@ -16,7 +16,9 @@ chip soc/intel/skylake
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD
# PL2 override 15W
- register "tdp_pl2_override" = "15"
+ register "power_limits_config" = "{
+ .tdp_pl2_override = 15,
+ }"
# Send an extra VR mailbox command for the supported MPS IMVP8 model
register "SendVrMbxCmd" = "1"
diff --git a/src/mainboard/google/glados/variants/glados/overridetree.cb b/src/mainboard/google/glados/variants/glados/overridetree.cb
index 1bc69abb17..c510e920a0 100644
--- a/src/mainboard/google/glados/variants/glados/overridetree.cb
+++ b/src/mainboard/google/glados/variants/glados/overridetree.cb
@@ -18,7 +18,9 @@ chip soc/intel/skylake
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 2
# PL2 override 15W
- register "tdp_pl2_override" = "15"
+ register "power_limits_config" = "{
+ .tdp_pl2_override = 15,
+ }"
# Send an extra VR mailbox command for the supported MPS IMVP8 model
register "SendVrMbxCmd" = "1"