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authorFelix Singer <felixsinger@posteo.net>2024-07-08 04:29:39 +0200
committerFelix Singer <felixsinger@posteo.net>2024-07-12 20:08:01 +0000
commit88bc0f1604494de0f87c6954c050e7ef4d1c4457 (patch)
tree9492b3a04b2bf7c66ac8202d97b3441d9ccf9306 /src/mainboard/google/glados
parent702902d71fae63fd35362c82f2a369b42af1a77f (diff)
skl/kbl mainboards: Move PCIe related settings into their device scope
Change-Id: I1ffa87eeee521180f37371e5a0d1f9a1a06091aa Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83373 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Diffstat (limited to 'src/mainboard/google/glados')
-rw-r--r--src/mainboard/google/glados/devicetree.cb10
1 files changed, 3 insertions, 7 deletions
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 88b7fbc49b..2d2e13cd52 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -41,13 +41,6 @@ chip soc/intel/skylake
register "PmConfigSlpSusMinAssert" = "3" # 4s
register "PmConfigSlpAMinAssert" = "3" # 2s
- # Enable Root port 1
- register "PcieRpEnable[0]" = "1"
- # Enable CLKREQ#
- register "PcieRpClkReqSupport[0]" = "1"
- # RP 1 uses SRCCLKREQ1#
- register "PcieRpClkReqNumber[0]" = "1"
-
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
@@ -85,6 +78,9 @@ chip soc/intel/skylake
device ref uart2 on end
device ref i2c4 on end
device ref pcie_rp1 on
+ register "PcieRpEnable[0]" = "1"
+ register "PcieRpClkReqSupport[0]" = "1"
+ register "PcieRpClkReqNumber[0]" = "1"
chip drivers/wifi/generic
register "wake" = "GPE0_DW0_16"
device pci 00.0 on end