diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-10-19 12:31:21 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-21 07:16:01 +0000 |
| commit | f50ea988b09e7201e129848ab64e6e0e69bf56c4 (patch) | |
| tree | e7cf17631d7c3cd41fa3c68a4c578d4ee7e36b8a /src/mainboard/google/glados/variants | |
| parent | dadcbfbe8c682c89b277fdbdfdd26cabd15fc20a (diff) | |
soc/intel,mb/*: get rid of legacy pad macros
Get rid of legacy pad macros by replacing them with their newer
equivalents.
TEST: TIMELESS-built board images match
Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/glados/variants')
7 files changed, 549 insertions, 549 deletions
diff --git a/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h index b6743dc47b..b4c65baa90 100644 --- a/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/asuka/include/variant/gpio.h @@ -48,138 +48,138 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), +/* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, UP_20K, DEEP), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* PCH_LPC_CLK */ PAD_CFG_NC(GPP_A10), -/* EC_HID_INT */ PAD_CFG_NC(GPP_A11), -/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), +/* PCH_LPC_CLK */ PAD_NC(GPP_A10, NONE), +/* EC_HID_INT */ PAD_NC(GPP_A11, NONE), +/* ISH_KB_PROX_INT */ PAD_NC(GPP_A12, NONE), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14), +/* PM_SUS_STAT */ PAD_NC(GPP_A14, NONE), /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), -/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), -/* SD_PWR_EN */ PAD_CFG_NC(GPP_A17), -/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20), -/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21), -/* GYRO_INT */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN */ PAD_NC(GPP_A17, NONE), +/* ACCEL INTERRUPT */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* GYRO_DRDY */ PAD_NC(GPP_A20, NONE), +/* FLIP_ACCEL_INT */ PAD_NC(GPP_A21, NONE), +/* GYRO_INT */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), /* HSJ_MIC_DET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B2, NONE, DEEP), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), -/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */ +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), +/* BT_RF_KILL */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* TOUCHPAD WAKE */ /* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), -/* SRCCLKREQ2 */ PAD_CFG_NC(GPP_B7), -/* AUDIO_INT_WAK */ PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES), -/* SRCCLKREQ4 */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11), +/* SRCCLKREQ2 */ PAD_NC(GPP_B7, NONE), +/* AUDIO_INT_WAK */ PAD_CFG_GPI_SCI(GPP_B8, NONE, DEEP, EDGE_SINGLE, INVERT), +/* SRCCLKREQ4 */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* MPHY_EXT_PWR_GATE */ PAD_NC(GPP_B11, NONE), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCH_BUZZER */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), -/* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -/* CCODEC_SPI_CS */ PAD_CFG_NC(GPP_B19), -/* CODEC_SPI_CLK */ PAD_CFG_NC(GPP_B20), -/* CODEC_SPI_MISO */ PAD_CFG_NC(GPP_B21), -/* CODEC_SPI_MOSI */ PAD_CFG_NC(GPP_B22), -/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), +/* SSD_PCIE_WAKE */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* CCODEC_SPI_CS */ PAD_NC(GPP_B19, NONE), +/* CODEC_SPI_CLK */ PAD_NC(GPP_B20, NONE), +/* CODEC_SPI_MISO */ PAD_NC(GPP_B21, NONE), +/* CODEC_SPI_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP), -/* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), -/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), +/* M2_WWAN_PWREN */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), /* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), -/* USB_CTL */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* NFC_RST* */ PAD_CFG_NC(GPP_C10), -/* EN_PP3300_KEPLER */ PAD_CFG_NC(GPP_C11), +/* USB_CTL */ PAD_NC(GPP_C7, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* NFC_RST* */ PAD_NC(GPP_C10, NONE), +/* EN_PP3300_KEPLER */ PAD_NC(GPP_C11, NONE), /* PCH_MEM_CFG0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* PCH_MEM_CFG1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* PCH_MEM_CFG2 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* PCH_MEM_CFG3 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, UP_5K, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, UP_5K, DEEP, NF1), /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP), -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), -/* ITCH_SPI_CS */ PAD_CFG_NC(GPP_D0), -/* ITCH_SPI_CLK */ PAD_CFG_NC(GPP_D1), -/* ITCH_SPI_MISO_1 */ PAD_CFG_NC(GPP_D2), -/* ITCH_SPI_MISO_0 */ PAD_CFG_NC(GPP_D3), -/* CAM_FLASH_STROBE */ PAD_CFG_NC(GPP_D4), -/* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5), -/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6), -/* SH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* SH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), +/* ITCH_SPI_CS */ PAD_NC(GPP_D0, NONE), +/* ITCH_SPI_CLK */ PAD_NC(GPP_D1, NONE), +/* ITCH_SPI_MISO_1 */ PAD_NC(GPP_D2, NONE), +/* ITCH_SPI_MISO_0 */ PAD_NC(GPP_D3, NONE), +/* CAM_FLASH_STROBE */ PAD_NC(GPP_D4, NONE), +/* EN_PP3300_DX_EMMC */ PAD_NC(GPP_D5, NONE), +/* EN_PP1800_DX_EMMC */ PAD_NC(GPP_D6, NONE), +/* SH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* SH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CSB */ PAD_NC(GPP_D9, NONE), /* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 0, DEEP), -/* EN_PP3300_DX_CAM */ PAD_CFG_NC(GPP_D12), -/* EN_PP1800_DX_AUDIO */PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK_1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA_1 */ PAD_CFG_NC(GPP_D18), +/* EN_PP3300_DX_CAM */ PAD_NC(GPP_D12, NONE), +/* EN_PP1800_DX_AUDIO */PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK_1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA_1 */ PAD_NC(GPP_D18, NONE), /* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21), -/* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22), +/* ITCH_SPI_D2 */ PAD_NC(GPP_D21, NONE), +/* ITCH_SPI_D3 */ PAD_NC(GPP_D22, NONE), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SSD_PEDET */ PAD_CFG_NC(GPP_E2), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SSD_PEDET */ PAD_NC(GPP_E2, NONE), /* AUDIO_DB_ID */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP), -/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), -/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* SSD_SATA_DEVSLP */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), -/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), +/* EC_SMI */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), +/* EC_SCI */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), -/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), -/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), -/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), -/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2S2_SCLK */ PAD_NC(GPP_F0, NONE), +/* I2S2_SFRM */ PAD_NC(GPP_F1, NONE), +/* I2S2_TXD */ PAD_NC(GPP_F2, NONE), +/* I2S2_RXD */ PAD_NC(GPP_F3, NONE), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), -/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), -/* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES), +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), +/* AUDIO_IRQ */ PAD_CFG_GPI_SCI(GPP_F11, NONE, DEEP, EDGE_SINGLE, INVERT), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -192,14 +192,14 @@ static const struct pad_config gpio_table[] = { /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* BOOT_BEEP */ PAD_CFG_GPO(GPP_F23, 0, DEEP), -/* SD_CMD */ PAD_CFG_NC(GPP_G0), -/* SD_DATA0 */ PAD_CFG_NC(GPP_G1), -/* SD_DATA1 */ PAD_CFG_NC(GPP_G2), -/* SD_DATA2 */ PAD_CFG_NC(GPP_G3), -/* SD_DATA3 */ PAD_CFG_NC(GPP_G4), -/* SD_CD# */ PAD_CFG_NC(GPP_G5), -/* SD_CLK */ PAD_CFG_NC(GPP_G6), -/* SD_WP */ PAD_CFG_NC(GPP_G7), +/* SD_CMD */ PAD_NC(GPP_G0, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), +/* SD_CD# */ PAD_NC(GPP_G5, NONE), +/* SD_CLK */ PAD_NC(GPP_G6, NONE), +/* SD_WP */ PAD_NC(GPP_G7, NONE), /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), @@ -207,16 +207,16 @@ static const struct pad_config gpio_table[] = { /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* GPD7 */ PAD_CFG_NC(GPD7), +/* GPD7 */ PAD_NC(GPD7, NONE), /* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* PCH_SLP_WLAN# */ PAD_CFG_NC(GPD9), -/* PM_SLP_S5# */ PAD_CFG_NC(GPD10), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* PCH_SLP_WLAN# */ PAD_NC(GPD9, NONE), +/* PM_SLP_S5# */ PAD_NC(GPD10, NONE), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), }; #endif diff --git a/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h b/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h index 1f4bd6565a..24e7b33cc2 100644 --- a/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h @@ -57,64 +57,64 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LAD0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LAD1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LAD2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LAD3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* PIRQA# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), /* SD_CD_INT_L */ +/* PIRQA# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, UP_20K, DEEP), /* SD_CD_INT_L */ /* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), -/* PME# */ PAD_CFG_NC(GPP_A11), -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), +/* PME# */ PAD_NC(GPP_A11, NONE), +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TOUCHPAD */ -/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */ +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CPU_GP2 */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* TOUCHPAD */ +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* TOUCHPAD WAKE */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN */ -/* SRCCLKREQ2# */ PAD_CFG_NC(GPP_B7), -/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), -/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11), +/* SRCCLKREQ2# */ PAD_NC(GPP_B7, NONE), +/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* EXT_PWR_GATE# */ PAD_NC(GPP_B11, NONE), /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* SPKR */ PAD_CFG_NC(GPP_B14), -/* GSPI0_CS# */ PAD_CFG_GPI_ACPI_SCI(GPP_B15, NONE, DEEP, NONE), /* DIG EJECT */ -/* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */ -/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), +/* SPKR */ PAD_NC(GPP_B14, NONE), +/* GSPI0_CS# */ PAD_CFG_GPI_SCI(GPP_B15, NONE, DEEP, EDGE_SINGLE, NONE), /* DIG EJECT */ +/* GSPI0_CLK */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), /* WLAN WAKE */ +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), /* GSPI1_CS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B19, NONE, DEEP), /* non-wake DIG EJECT */ -/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), -/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), -/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), -/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */ /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */ -/* SMBALERT# */ PAD_CFG_NC(GPP_C2), -/* SML0CLK */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), -/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ -/* SM1DATA */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), +/* SMBALERT# */ PAD_NC(GPP_C2, NONE), +/* SML0CLK */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ +/* SM1DATA */ PAD_NC(GPP_C7, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_RTS# */ PAD_NC(GPP_C10, NONE), /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_DX_DIG */ /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ /* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ @@ -127,55 +127,55 @@ static const struct pad_config gpio_table[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ -/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), -/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ +/* SPI1_CS# */ PAD_NC(GPP_D0, NONE), +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* ISH_I2C0_SDA */ PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */ /* ISH_I2C0_SCL */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */ -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CS# */ PAD_CFG_NC(GPP_D9), -/* ISH_SPI_CLK */ PAD_CFG_NC(GPP_D10), -/* ISH_SPI_MISO */ PAD_CFG_NC(GPP_D11), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CS# */ PAD_NC(GPP_D9, NONE), +/* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE), +/* ISH_SPI_MISO */ PAD_NC(GPP_D11, NONE), /* ISH_SPI_MOSI */ PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE), /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* TS_SPI1_IO2 */ PAD_CFG_NC(GPP_D21), +/* TS_SPI1_IO2 */ PAD_NC(GPP_D21, NONE), /* TS_SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 1, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), -/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN */ -/* SATALED# */ PAD_CFG_NC(GPP_E8), -/* USB2_OCO# */ PAD_CFG_NC(GPP_E9), -/* USB2_OC1# */ PAD_CFG_NC(GPP_E10), +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SATAXPCIE2 */ PAD_NC(GPP_E2, NONE), +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* CPU_GP1 */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN */ +/* SATALED# */ PAD_NC(GPP_E8, NONE), +/* USB2_OCO# */ PAD_NC(GPP_E9, NONE), +/* USB2_OC1# */ PAD_NC(GPP_E10, NONE), /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */ -/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */ +/* DDPD_HPD2 */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SMI_L */ +/* DDPE_HPD3 */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SCI_L */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), -/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19), -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), -/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21), -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), -/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), +/* DDPB_CTRLCLK */ PAD_NC(GPP_E18, NONE), +/* DDPB_CTRLDATA */ PAD_NC(GPP_E19, NONE), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), +/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), /* * The next 4 pads are for bit banging the amplifiers. They are connected * together with i2s0 signals. For default behavior of i2s make these @@ -187,12 +187,12 @@ static const struct pad_config gpio_table[] = { /* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP), /* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* DIG */ /* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* DIG */ -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_GPI_APIC(GPP_F7, NONE, PLTRST), /* DIG_PDCT_L */ +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_CFG_GPI_APIC_HIGH(GPP_F7, NONE, PLTRST), /* DIG_PDCT_L */ /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* Amplifiers */ /* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* Amplifiers */ -/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ -/* I2C5_SCL */ PAD_CFG_GPI_APIC(GPP_F11, NONE, PLTRST), /* DIG_IRQ_L */ +/* I2C5_SDA */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ +/* I2C5_SCL */ PAD_CFG_GPI_APIC_HIGH(GPP_F11, NONE, PLTRST), /* DIG_IRQ_L */ /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -204,7 +204,7 @@ static const struct pad_config gpio_table[] = { /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* RSVD */ PAD_CFG_NC(GPP_F23), +/* RSVD */ PAD_NC(GPP_F23, NONE), /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), /* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), @@ -216,7 +216,7 @@ static const struct pad_config gpio_table[] = { * SD write protect is not connected but is still sampled, so enable * native function and enable internal pull-down to disable. */ -/* SD_WP */ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */ @@ -224,16 +224,16 @@ static const struct pad_config gpio_table[] = { /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* RSVD */ PAD_CFG_NC(GPD7), +/* RSVD */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* SLP_WLAN# */ PAD_CFG_NC(GPD9), -/* SLP_S5# */ PAD_CFG_NC(GPD10), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* SLP_WLAN# */ PAD_NC(GPD9, NONE), +/* SLP_S5# */ PAD_NC(GPD10, NONE), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ }; #endif diff --git a/src/mainboard/google/glados/variants/cave/include/variant/gpio.h b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h index e1c2d585fe..7d000f5d6e 100644 --- a/src/mainboard/google/glados/variants/cave/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/cave/include/variant/gpio.h @@ -53,65 +53,65 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LAD0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LAD1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LAD2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LAD3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* SD_CD_INT_L */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), +/* SD_CD_INT_L */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, UP_20K, DEEP), /* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), -/* PME# */ PAD_CFG_NC(GPP_A11), -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), +/* PME# */ PAD_NC(GPP_A11, NONE), +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TRACKPAD */ -/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TRACKPAD WAKE */ +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), +/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CPU_GP2 */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* TRACKPAD */ +/* CPU_GP3 */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* TRACKPAD WAKE */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN */ -/* SRCCLKREQ2# */ PAD_CFG_NC(GPP_B7), -/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), -/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), +/* SRCCLKREQ2# */ PAD_NC(GPP_B7, NONE), +/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* SPKR */ PAD_CFG_NC(GPP_B14), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */ -/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), -/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), -/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), -/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), +/* SPKR */ PAD_NC(GPP_B14, NONE), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* GSPI0_CLK */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), /* WLAN WAKE */ +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), +/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* SM1ALERT# */ PAD_CFG_GPO(GPP_B23, 0, DEEP), /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */ /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */ -/* SMBALERT# */ PAD_CFG_NC(GPP_C2), +/* SMBALERT# */ PAD_NC(GPP_C2, NONE), /* SML0CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C3, NONE, DEEP), /* SML0DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C4, NONE, DEEP), /* SML0ALERT# */ PAD_CFG_GPO(GPP_C5, 0, DEEP), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ /* SM1DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C7, NONE, DEEP), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), -/* UART0_CTS# */ PAD_CFG_NC(GPP_C11), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_RTS# */ PAD_NC(GPP_C10, NONE), +/* UART0_CTS# */ PAD_NC(GPP_C11, NONE), /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ /* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ /* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */ @@ -123,55 +123,55 @@ static const struct pad_config gpio_table[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ -/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), -/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), -/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), -/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ +/* SPI1_CS# */ PAD_NC(GPP_D0, NONE), +/* SPI1_CLK */ PAD_NC(GPP_D1, NONE), +/* SPI1_MISO */ PAD_NC(GPP_D2, NONE), +/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE), +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* ISH_I2C0_SDA */ PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */ /* ISH_I2C0_SCL */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */ -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), - PAD_CFG_NC(GPP_D9), - PAD_CFG_NC(GPP_D10), - PAD_CFG_NC(GPP_D11), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE), /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* TS_SPI_IO2 */ PAD_CFG_NC(GPP_D21), -/* TS_SPI_IO3 */ PAD_CFG_NC(GPP_D22), +/* TS_SPI_IO2 */ PAD_NC(GPP_D21, NONE), +/* TS_SPI_IO3 */ PAD_NC(GPP_D22, NONE), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SATAXPCIE2 */ PAD_NC(GPP_E2, NONE), /* CPU_GP0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP), /* AUDIO_DB_ID */ /* SATA_DEVSLP0 */ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* TOUCH_RESET */ -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN */ -/* SATALED# */ PAD_CFG_NC(GPP_E8), -/* USB2_OCO# */ PAD_CFG_NC(GPP_E9), -/* USB2_OC1# */ PAD_CFG_NC(GPP_E10), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* CPU_GP1 */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN */ +/* SATALED# */ PAD_NC(GPP_E8, NONE), +/* USB2_OCO# */ PAD_NC(GPP_E9, NONE), +/* USB2_OC1# */ PAD_NC(GPP_E10, NONE), /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */ -/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */ +/* DDPD_HPD2 */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SMI_L */ +/* DDPE_HPD3 */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SCI_L */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), +/* DDPB_CTRLCLK */ PAD_NC(GPP_E18, NONE), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), - PAD_CFG_NC(GPP_E22), - PAD_CFG_NC(GPP_E23), + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), /* * The next 4 pads are for bit banging the amplifiers. They are connected * together with i2s0 signals. For default behavior of i2s make these @@ -181,14 +181,14 @@ static const struct pad_config gpio_table[] = { /* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP), /* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* Amplifiers */ /* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* Amplifiers */ -/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ -/* I2C5_SCL */ PAD_CFG_NC(GPP_F11), +/* I2C5_SDA */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ +/* I2C5_SCL */ PAD_NC(GPP_F11, NONE), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -208,24 +208,24 @@ static const struct pad_config gpio_table[] = { /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* SD_WP */ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), -/* LAN_WAKE# */ PAD_CFG_NF(GPD2, 20K_PU, DEEP, NF1), /* EC_PCH_WAKE_L */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), -/* SLP_S3# */ PAD_CFG_NF(GPD4, 20K_PU, DEEP, NF1), -/* SLP_S4# */ PAD_CFG_NF(GPD5, 20K_PU, DEEP, NF1), -/* SLP_A# */ PAD_CFG_NF(GPD6, 20K_PU, DEEP, NF1), - PAD_CFG_NC(GPD7), +/* LAN_WAKE# */ PAD_CFG_NF(GPD2, UP_20K, DEEP, NF1), /* EC_PCH_WAKE_L */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), +/* SLP_S3# */ PAD_CFG_NF(GPD4, UP_20K, DEEP, NF1), +/* SLP_S4# */ PAD_CFG_NF(GPD5, UP_20K, DEEP, NF1), +/* SLP_A# */ PAD_CFG_NF(GPD6, UP_20K, DEEP, NF1), + PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* SLP_WLAN# */ PAD_CFG_NC(GPD9), -/* SLP_S5# */ PAD_CFG_NF(GPD10, 20K_PU, DEEP, NF1), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* SLP_WLAN# */ PAD_NC(GPD9, NONE), +/* SLP_S5# */ PAD_CFG_NF(GPD10, UP_20K, DEEP, NF1), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ }; #endif diff --git a/src/mainboard/google/glados/variants/chell/include/variant/gpio.h b/src/mainboard/google/glados/variants/chell/include/variant/gpio.h index 06c6e4a8f7..6d415ca30a 100644 --- a/src/mainboard/google/glados/variants/chell/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/chell/include/variant/gpio.h @@ -47,51 +47,51 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LAD0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LAD1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LAD2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LAD3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* PIRQA# */ PAD_CFG_NC(GPP_A7), +/* PIRQA# */ PAD_NC(GPP_A7, NONE), /* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), +/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* PME# */ PAD_CFG_GPO(GPP_A11, 0, DEEP), -/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* BM_BUSY# */ PAD_NC(GPP_A12, NONE), /* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* SUS_STAT# */ PAD_CFG_GPO(GPP_A14, 0, DEEP), /* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), -/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), -/* SD_PWR_EN# */ PAD_CFG_NC(GPP_A17), -/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), +/* ISH_GP0 */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* ISH_GP2 */ PAD_NC(GPP_A20, NONE), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), +/* ISH_GP4 */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), /* CORE_VID0 */ PAD_CFG_GPO(GPP_B0, 0, DEEP), /* CORE_VID1 */ PAD_CFG_GPO(GPP_B1, 0, DEEP), -/* VRALERT# */ PAD_CFG_NC(GPP_B2), -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TRACKPAD_INT_L */ +/* VRALERT# */ PAD_NC(GPP_B2, NONE), +/* CPU_GP2 */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* TRACKPAD_INT_L */ /* CPU_GP3 */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* TOUCHSCREEN_EN */ -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TRACKPAD WAKE */ +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* TRACKPAD WAKE */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CKLREQ */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER CLKREQ */ -/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), -/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11), +/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE), +/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* EXT_PWR_GATE# */ PAD_NC(GPP_B11, NONE), /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* SPKR */ PAD_CFG_GPO(GPP_B14, 0, DEEP), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */ -/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* GSPI0_CLK */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), /* WLAN WAKE */ +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* GSPI0_MOSI */ PAD_CFG_GPO(GPP_B18, 0, DEEP), -/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), -/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), -/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), +/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), +/* GSPI1_MISO */ PAD_NC(GPP_B21, NONE), /* GSPI1_MOSI */ PAD_CFG_GPO(GPP_B22, 0, DEEP), /* SM1ALERT# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B23, NONE, DEEP), /* UNUSED */ /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */ @@ -100,11 +100,11 @@ static const struct pad_config gpio_table[] = { /* SML0CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C3, NONE, DEEP), /* UNUSED */ /* SML0DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C4, NONE, DEEP), /* UNUSED */ /* SML0ALERT# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C5, NONE, DEEP), /* UNUSED */ -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ /* SM1DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C7, NONE, DEEP), /* UNUSED */ -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_RTS# */ PAD_NC(GPP_C10, NONE), /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ /* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ /* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ @@ -117,55 +117,55 @@ static const struct pad_config gpio_table[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ /* SPI1_CS# */ PAD_CFG_GPO(GPP_D0, 0, DEEP), /* SPI1_CLK */ PAD_CFG_GPO(GPP_D1, 0, DEEP), /* SPI1_MISO */ PAD_CFG_GPO(GPP_D2, 0, DEEP), /* SPI1_MOSI */ PAD_CFG_GPO(GPP_D3, 0, DEEP), -/* FASHTRIG */ PAD_CFG_NC(GPP_D4), +/* FASHTRIG */ PAD_NC(GPP_D4, NONE), /* ISH_I2C0_SDA */ PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */ /* ISH_I2C0_SCL */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */ -/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CS# */ PAD_CFG_NC(GPP_D9), +/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CS# */ PAD_NC(GPP_D9, NONE), /* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* USBA_1_ILIM_SEL_L */ -/* ISH_SPI_MISO */ PAD_CFG_NC(GPP_D11), +/* ISH_SPI_MISO */ PAD_NC(GPP_D11, NONE), /* ISH_SPI_MOSI */ PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */ -/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), -/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), -/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), +/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE), +/* DMIC_CLK1 */ PAD_NC(GPP_D17, NONE), +/* DMIC_DATA1 */ PAD_NC(GPP_D18, NONE), /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */ +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SATAXPCIE2 */ PAD_NC(GPP_E2, NONE), /* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, DEEP), /* TOUCHSCREEN_RST_L */ -/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */ -/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* CPU_GP1 */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */ +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USBA_OC0_L */ -/* USB2_OC1# */ PAD_CFG_NC(GPP_E10), +/* USB2_OC1# */ PAD_NC(GPP_E10, NONE), /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USBC_OC2_L */ /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* USBC_OC3_L */ /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* USB_C0_DP_HPD */ /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* USB_C1_DP_HPD */ -/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */ -/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */ +/* DDPD_HPD2 */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SMI_L */ +/* DDPE_HPD3 */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SCI_L */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_GPO(GPP_E18, 0, DEEP), -/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19), /* External pullup */ -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), -/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21), /* External pullup. */ -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), -/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), +/* DDPB_CTRLDATA */ PAD_NC(GPP_E19, NONE), /* External pullup */ +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), +/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE), /* External pullup. */ +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), +/* DDPD_CTRLDATA */ PAD_NC(GPP_E23, NONE), /* * The next 4 pads are for bit banging the amplifiers. They are connected * together with i2s0 signals. For default behavior of i2s make these @@ -175,13 +175,13 @@ static const struct pad_config gpio_table[] = { /* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP), /* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */ /* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */ -/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ +/* I2C5_SDA */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ /* I2C5_SCL */ PAD_CFG_GPO(GPP_F11, 0, DEEP), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), @@ -194,15 +194,15 @@ static const struct pad_config gpio_table[] = { /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* RSVD */ PAD_CFG_NC(GPP_F23), -/* SD_CMD */ PAD_CFG_NC(GPP_G0), -/* SD_DATA0 */ PAD_CFG_NC(GPP_G1), -/* SD_DATA1 */ PAD_CFG_NC(GPP_G2), -/* SD_DATA2 */ PAD_CFG_NC(GPP_G3), -/* SD_DATA3 */ PAD_CFG_NC(GPP_G4), -/* SD_CD# */ PAD_CFG_NC(GPP_G5), -/* SD_CLK */ PAD_CFG_NC(GPP_G6), -/* SD_WP */ PAD_CFG_NC(GPP_G7), +/* RSVD */ PAD_NC(GPP_F23, NONE), +/* SD_CMD */ PAD_NC(GPP_G0, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), +/* SD_CD# */ PAD_NC(GPP_G5, NONE), +/* SD_CLK */ PAD_NC(GPP_G6, NONE), +/* SD_WP */ PAD_NC(GPP_G7, NONE), /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */ @@ -210,18 +210,18 @@ static const struct pad_config gpio_table[] = { /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SLP_A# */ PAD_CFG_GPO(GPD6, 0, DEEP), -/* RSVD */ PAD_CFG_NC(GPD7), +/* RSVD */ PAD_NC(GPD7, NONE), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SLP_WLAN# */ PAD_CFG_GPO(GPD9, 0, DEEP), /* SLP_S5# */ PAD_CFG_GPO(GPD10, 0, DEEP), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ }; #endif diff --git a/src/mainboard/google/glados/variants/glados/include/variant/gpio.h b/src/mainboard/google/glados/variants/glados/include/variant/gpio.h index 5361744407..9ee00d2cf9 100644 --- a/src/mainboard/google/glados/variants/glados/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/glados/include/variant/gpio.h @@ -44,10 +44,10 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LAD0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LAD1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LAD2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LAD3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* PIRQA# */ /* GPP_A7 */ @@ -70,7 +70,7 @@ static const struct pad_config gpio_table[] = { /* CORE_VID0 */ /* GPP_B0 */ /* CORE_VID1 */ /* GPP_B1 */ /* VRALERT# */ /* GPP_B2 */ -/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), /* TRACKPAD */ +/* CPU_GP2 */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, DEEP), /* TRACKPAD */ /* CPU_GP3 */ /* GPP_B4 */ /* SRCCLKREQ0# */ /* GPP_B5 */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN */ @@ -83,7 +83,7 @@ static const struct pad_config gpio_table[] = { /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* SPKR */ /* GPP_B14 */ /* GSPI0_CS# */ /* GPP_B15 */ -/* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */ +/* GSPI0_CLK */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), /* WLAN WAKE */ /* GSPI0_MISO */ /* GPP_B17 */ /* GSPI0_MOSI */ /* GPP_B18 */ /* GSPI1_CS# */ /* GPP_B19 */ @@ -97,7 +97,7 @@ static const struct pad_config gpio_table[] = { /* SML0CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C3, NONE, DEEP), /* SML0DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C4, NONE, DEEP), /* SML0ALERT# */ PAD_CFG_GPO(GPP_C5, 0, DEEP), -/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */ /* SM1DATA */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C7, NONE, DEEP), /* UART0_RXD */ /* GPP_C8 */ @@ -119,7 +119,7 @@ static const struct pad_config gpio_table[] = { /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */ -/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */ /* GPP_D0 */ /* GPP_D1 */ @@ -145,14 +145,14 @@ static const struct pad_config gpio_table[] = { /* GPP_D21 */ /* GPP_D22 */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), /* TPM_PIRQ_L */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, DEEP), /* TPM_PIRQ_L */ /* SATAXPCIE1 */ /* GPP_E1 */ /* SATAXPCIE2 */ /* GPP_E2 */ /* CPU_GP0 */ /* GPP_E3 */ /* SATA_DEVSLP0 */ /* GPP_E4 */ /* SATA_DEVSLP1 */ /* GPP_E5 */ /* SATA_DEVSLP2 */ /* GPP_E6 */ -/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), /* TOUCHSCREEN */ +/* CPU_GP1 */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, DEEP), /* TOUCHSCREEN */ /* SATALED# */ /* GPP_E8 */ /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), @@ -160,8 +160,8 @@ static const struct pad_config gpio_table[] = { /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */ -/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */ +/* DDPD_HPD2 */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SMI_L */ +/* DDPE_HPD3 */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SCI_L */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ /* GPP_E18 */ /* DDPB_CTRLDATA */ /* GPP_E19 */ @@ -184,7 +184,7 @@ static const struct pad_config gpio_table[] = { /* I2C3_SCL */ /* GPP_F7 */ /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* Amplifiers */ /* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* Amplifiers */ -/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), /* MIC_INT_L */ +/* I2C5_SDA */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, DEEP), /* MIC_INT_L */ /* I2C5_SCL */ /* GPP_F11 */ /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), diff --git a/src/mainboard/google/glados/variants/lars/include/variant/gpio.h b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h index d1785cea3c..3d00c353d7 100644 --- a/src/mainboard/google/glados/variants/lars/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/lars/include/variant/gpio.h @@ -43,124 +43,124 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* PIRQA# */ PAD_CFG_NC(GPP_A7), +/* PIRQA# */ PAD_NC(GPP_A7, NONE), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* PCH_LPC_CLK */ PAD_CFG_NC(GPP_A10), -/* EC_HID_INT */ PAD_CFG_NC(GPP_A11), -/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), +/* PCH_LPC_CLK */ PAD_NC(GPP_A10, NONE), +/* EC_HID_INT */ PAD_NC(GPP_A11, NONE), +/* ISH_KB_PROX_INT */ PAD_NC(GPP_A12, NONE), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14), +/* PM_SUS_STAT */ PAD_NC(GPP_A14, NONE), /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), -/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), -/* SD_PWR_EN */ PAD_CFG_NC(GPP_A17), -/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20), -/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21), -/* GYRO_INT */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), +/* SD_PWR_EN */ PAD_NC(GPP_A17, NONE), +/* ACCEL INTERRUPT */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* GYRO_DRDY */ PAD_NC(GPP_A20, NONE), +/* FLIP_ACCEL_INT */ PAD_NC(GPP_A21, NONE), +/* GYRO_INT */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), /* HSJ_MIC_DET */ PAD_CFG_GPO(GPP_B2, 0, DEEP), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), -/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */ +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), +/* BT_RF_KILL */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* TOUCHPAD WAKE */ /* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), -/* KEPLR_CLK_REQ */ PAD_CFG_NC(GPP_B7), -/* AUDIO_INT_WAK */ PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES), -/* SSD_CLK_REQ */ PAD_CFG_NC(GPP_B9), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11), +/* KEPLR_CLK_REQ */ PAD_NC(GPP_B7, NONE), +/* AUDIO_INT_WAK */ PAD_CFG_GPI_SCI(GPP_B8, NONE, DEEP, EDGE_SINGLE, INVERT), +/* SSD_CLK_REQ */ PAD_NC(GPP_B9, NONE), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* MPHY_EXT_PWR_GATE */ PAD_NC(GPP_B11, NONE), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCH_BUZZER */ PAD_CFG_GPO(GPP_B14, 0, DEEP), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), -/* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -/* CCODEC_SPI_CS */ PAD_CFG_NC(GPP_B19), -/* CODEC_SPI_CLK */ PAD_CFG_NC(GPP_B20), -/* CODEC_SPI_MISO */ PAD_CFG_NC(GPP_B21), -/* CODEC_SPI_MOSI */ PAD_CFG_NC(GPP_B22), -/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), +/* SSD_PCIE_WAKE */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* CCODEC_SPI_CS */ PAD_NC(GPP_B19, NONE), +/* CODEC_SPI_CLK */ PAD_NC(GPP_B20, NONE), +/* CODEC_SPI_MISO */ PAD_NC(GPP_B21, NONE), +/* CODEC_SPI_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP), -/* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), -/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), +/* M2_WWAN_PWREN */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), /* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), -/* USB_CTL */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* NFC_RST* */ PAD_CFG_NC(GPP_C10), -/* EN_PP3300_KEPLER */ PAD_CFG_NC(GPP_C11), +/* USB_CTL */ PAD_NC(GPP_C7, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* NFC_RST* */ PAD_NC(GPP_C10, NONE), +/* EN_PP3300_KEPLER */ PAD_NC(GPP_C11, NONE), /* PCH_MEM_CFG0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* PCH_MEM_CFG1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* PCH_MEM_CFG2 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* PCH_MEM_CFG3 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, UP_5K, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, UP_5K, DEEP, NF1), /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP), -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), -/* ITCH_SPI_CS */ PAD_CFG_NC(GPP_D0), -/* ITCH_SPI_CLK */ PAD_CFG_NC(GPP_D1), -/* ITCH_SPI_MISO_1 */ PAD_CFG_NC(GPP_D2), -/* ITCH_SPI_MISO_0 */ PAD_CFG_NC(GPP_D3), -/* CAM_FLASH_STROBE */ PAD_CFG_NC(GPP_D4), -/* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5), -/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6), -/* SH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* SH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), +/* ITCH_SPI_CS */ PAD_NC(GPP_D0, NONE), +/* ITCH_SPI_CLK */ PAD_NC(GPP_D1, NONE), +/* ITCH_SPI_MISO_1 */ PAD_NC(GPP_D2, NONE), +/* ITCH_SPI_MISO_0 */ PAD_NC(GPP_D3, NONE), +/* CAM_FLASH_STROBE */ PAD_NC(GPP_D4, NONE), +/* EN_PP3300_DX_EMMC */ PAD_NC(GPP_D5, NONE), +/* EN_PP1800_DX_EMMC */ PAD_NC(GPP_D6, NONE), +/* SH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* SH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CSB */ PAD_NC(GPP_D9, NONE), /* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 0, DEEP), -/* EN_PP3300_DX_CAM */ PAD_CFG_NC(GPP_D12), +/* EN_PP3300_DX_CAM */ PAD_NC(GPP_D12, NONE), /* EN_PP1800_DX_AUDIO */PAD_CFG_GPO(GPP_D13, 1, DEEP), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS */ PAD_NC(GPP_D16, NONE), /* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21), -/* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22), +/* ITCH_SPI_D2 */ PAD_NC(GPP_D21, NONE), +/* ITCH_SPI_D3 */ PAD_NC(GPP_D22, NONE), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SSD_PEDET */ PAD_CFG_NC(GPP_E2), -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), -/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), -/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SSD_PEDET */ PAD_NC(GPP_E2, NONE), +/* CPU_GP0 */ PAD_NC(GPP_E3, NONE), +/* SSD_SATA_DEVSLP */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), -/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), +/* EC_SMI */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), +/* EC_SCI */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), /* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), /* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP), @@ -168,12 +168,12 @@ static const struct pad_config gpio_table[] = { /* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP), /* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), -/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), -/* I2C5_SCL */ PAD_CFG_NC(GPP_F11), +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), +/* I2C5_SCL */ PAD_NC(GPP_F11, NONE), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -186,14 +186,14 @@ static const struct pad_config gpio_table[] = { /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* BOOT_BEEP */ PAD_CFG_GPO(GPP_F23, 0, DEEP), -/* SD_CMD */ PAD_CFG_NC(GPP_G0), -/* SD_DATA0 */ PAD_CFG_NC(GPP_G1), -/* SD_DATA1 */ PAD_CFG_NC(GPP_G2), -/* SD_DATA2 */ PAD_CFG_NC(GPP_G3), -/* SD_DATA3 */ PAD_CFG_NC(GPP_G4), -/* SD_CD# */ PAD_CFG_NC(GPP_G5), -/* SD_CLK */ PAD_CFG_NC(GPP_G6), -/* SD_WP */ PAD_CFG_NC(GPP_G7), +/* SD_CMD */ PAD_NC(GPP_G0, NONE), +/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), +/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), +/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), +/* SD_DATA3 */ PAD_NC(GPP_G4, NONE), +/* SD_CD# */ PAD_NC(GPP_G5, NONE), +/* SD_CLK */ PAD_NC(GPP_G6, NONE), +/* SD_WP */ PAD_NC(GPP_G7, NONE), /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), @@ -201,18 +201,18 @@ static const struct pad_config gpio_table[] = { /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* GPD7 */ PAD_CFG_NC(GPD7), +/* GPD7 */ PAD_NC(GPD7, NONE), /* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* PCH_SLP_WLAN# */ PAD_CFG_NC(GPD9), -/* PM_SLP_S5# */ PAD_CFG_NC(GPD10), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* PCH_SLP_WLAN# */ PAD_NC(GPD9, NONE), +/* PM_SLP_S5# */ PAD_NC(GPD10, NONE), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), }; #endif diff --git a/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h index 60d93d4308..717e930d24 100644 --- a/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h +++ b/src/mainboard/google/glados/variants/sentry/include/variant/gpio.h @@ -51,137 +51,137 @@ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), +/* SD_CD_WAKE */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, UP_20K, DEEP), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* PCH_LPC_CLK */ PAD_CFG_NC(GPP_A10), -/* EC_HID_INT */ PAD_CFG_NC(GPP_A11), -/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), +/* PCH_LPC_CLK */ PAD_NC(GPP_A10, NONE), +/* EC_HID_INT */ PAD_NC(GPP_A11, NONE), +/* ISH_KB_PROX_INT */ PAD_NC(GPP_A12, NONE), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14), +/* PM_SUS_STAT */ PAD_NC(GPP_A14, NONE), /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20), -/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21), -/* GYRO_INT */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* ACCEL INTERRUPT */ PAD_NC(GPP_A18, NONE), +/* ISH_GP1 */ PAD_NC(GPP_A19, NONE), +/* GYRO_DRDY */ PAD_NC(GPP_A20, NONE), +/* FLIP_ACCEL_INT */ PAD_NC(GPP_A21, NONE), +/* GYRO_INT */ PAD_NC(GPP_A22, NONE), +/* ISH_GP5 */ PAD_NC(GPP_A23, NONE), +/* CORE_VID0 */ PAD_NC(GPP_B0, NONE), +/* CORE_VID1 */ PAD_NC(GPP_B1, NONE), /* HSJ_MIC_DET */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B2, NONE, DEEP), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), -/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), -/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), +/* BT_RF_KILL */ PAD_NC(GPP_B4, NONE), +/* SRCCLKREQ0# */ PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), -/* AUDIO_INT_WAK */ PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES), +/* AUDIO_INT_WAK */ PAD_CFG_GPI_SCI(GPP_B8, NONE, DEEP, EDGE_SINGLE, INVERT), /* SSD_CLK_REQ */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), +/* MPHY_EXT_PWR_GATE */ PAD_NC(GPP_B11, NONE), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCH_BUZZER */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B14, NONE, DEEP), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), -/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), -/* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -/* CCODEC_SPI_CS */ PAD_CFG_NC(GPP_B19), -/* CODEC_SPI_CLK */ PAD_CFG_NC(GPP_B20), -/* CODEC_SPI_MISO */ PAD_CFG_NC(GPP_B21), -/* CODEC_SPI_MOSI */ PAD_CFG_NC(GPP_B22), -/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), +/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), +/* SSD_PCIE_WAKE */ PAD_NC(GPP_B17, NONE), +/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), +/* CCODEC_SPI_CS */ PAD_NC(GPP_B19, NONE), +/* CODEC_SPI_CLK */ PAD_NC(GPP_B20, NONE), +/* CODEC_SPI_MISO */ PAD_NC(GPP_B21, NONE), +/* CODEC_SPI_MOSI */ PAD_NC(GPP_B22, NONE), +/* SM1ALERT# */ PAD_NC(GPP_B23, NONE), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP), -/* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), -/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), +/* M2_WWAN_PWREN */ PAD_NC(GPP_C3, NONE), +/* SML0DATA */ PAD_NC(GPP_C4, NONE), +/* SML0ALERT# */ PAD_NC(GPP_C5, NONE), /* EC_IN_RW */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, NONE, DEEP), -/* USB_CTL */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* NFC_RST* */ PAD_CFG_NC(GPP_C10), -/* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 0, 20K_PD, DEEP), +/* USB_CTL */ PAD_NC(GPP_C7, NONE), +/* UART0_RXD */ PAD_NC(GPP_C8, NONE), +/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* NFC_RST* */ PAD_NC(GPP_C10, NONE), +/* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 0, DN_20K, DEEP), /* PCH_MEM_CFG0 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* PCH_MEM_CFG1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* PCH_MEM_CFG2 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP), /* PCH_MEM_CFG3 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, UP_5K, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, UP_5K, DEEP, NF1), /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP), -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), -/* ITCH_SPI_CS */ PAD_CFG_NC(GPP_D0), -/* ITCH_SPI_CLK */ PAD_CFG_NC(GPP_D1), -/* ITCH_SPI_MISO_1 */ PAD_CFG_NC(GPP_D2), -/* ITCH_SPI_MISO_0 */ PAD_CFG_NC(GPP_D3), -/* CAM_FLASH_STROBE */ PAD_CFG_NC(GPP_D4), -/* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5), -/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6), -/* SH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* SH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), +/* ITCH_SPI_CS */ PAD_NC(GPP_D0, NONE), +/* ITCH_SPI_CLK */ PAD_NC(GPP_D1, NONE), +/* ITCH_SPI_MISO_1 */ PAD_NC(GPP_D2, NONE), +/* ITCH_SPI_MISO_0 */ PAD_NC(GPP_D3, NONE), +/* CAM_FLASH_STROBE */ PAD_NC(GPP_D4, NONE), +/* EN_PP3300_DX_EMMC */ PAD_NC(GPP_D5, NONE), +/* EN_PP1800_DX_EMMC */ PAD_NC(GPP_D6, NONE), +/* SH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), +/* SH_I2C1_SCL */ PAD_NC(GPP_D8, NONE), +/* ISH_SPI_CSB */ PAD_NC(GPP_D9, NONE), /* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 0, DEEP), -/* EN_PP3300_DX_CAM */ PAD_CFG_NC(GPP_D12), -/* EN_PP1800_DX_AUDIO */PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16), +/* EN_PP3300_DX_CAM */ PAD_NC(GPP_D12, NONE), +/* EN_PP1800_DX_AUDIO */PAD_NC(GPP_D13, NONE), +/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE), +/* ISH_UART0_RTS */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_CTS */ PAD_NC(GPP_D16, NONE), /* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21), -/* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22), +/* ITCH_SPI_D2 */ PAD_NC(GPP_D21, NONE), +/* ITCH_SPI_D3 */ PAD_NC(GPP_D22, NONE), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SSD_PEDET */ PAD_CFG_NC(GPP_E2), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), +/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), +/* SSD_PEDET */ PAD_NC(GPP_E2, NONE), /* AUDIO_DB_ID */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP), -/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), -/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), -/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* SSD_SATA_DEVSLP */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE), +/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE), +/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), +/* SATALED# */ PAD_NC(GPP_E8, NONE), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), -/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), +/* EC_SMI */ PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), +/* EC_SCI */ PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), +/* DDPB_CTRLCLK */ PAD_NC(GPP_E18, NONE), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), +/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE), /* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE), /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), /* I2S2_SCLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP), /* I2S2_SFRM */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP), /* I2S2_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP), /* I2S2_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C2_SDA */ PAD_NC(GPP_F4, NONE), +/* I2C2_SCL */ PAD_NC(GPP_F5, NONE), +/* I2C3_SDA */ PAD_NC(GPP_F6, NONE), +/* I2C3_SCL */ PAD_NC(GPP_F7, NONE), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), -/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), -/* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES), +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), +/* AUDIO_IRQ */ PAD_CFG_GPI_SCI(GPP_F11, NONE, DEEP, EDGE_SINGLE, INVERT), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -201,7 +201,7 @@ static const struct pad_config gpio_table[] = { /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* SD_WP */ PAD_CFG_NF(GPP_G7, 20K_PU, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, UP_20K, DEEP, NF1), /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), @@ -209,17 +209,17 @@ static const struct pad_config gpio_table[] = { /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* GPD7 */ PAD_CFG_NC(GPD7), +/* GPD7 */ PAD_NC(GPD7, NONE), /* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* PCH_SLP_WLAN# */ PAD_CFG_NC(GPD9), -/* PM_SLP_S5# */ PAD_CFG_NC(GPD10), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* PCH_SLP_WLAN# */ PAD_NC(GPD9, NONE), +/* PM_SLP_S5# */ PAD_NC(GPD10, NONE), +/* LANPHYC */ PAD_NC(GPD11, NONE), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ -/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), +/* SPI_WP_STATUS */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ }; |