diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-10-09 21:02:36 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-21 14:23:21 +0000 |
| commit | f89cb241eecdf70d9e52c852833c6ed1e3b9632d (patch) | |
| tree | 3f8ab425bf8a78f517c17f41598e0c60a390c18b /src/mainboard/google/glados/variants/lars/variant.c | |
| parent | 24ba85002a5eb49c501888338a84308835b340ab (diff) | |
mb/google/glados: port to FSP 2.0
This patch is part of the patch series to drop support for FSP 1.1 in
soc/intel/skylake.
The following modifications have been done to migrate the board(s) from
FSP 1.1 to FSP 2.0:
- remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0)
- switch to using the FSP default VBT
TODO:
- testing
Change-Id: Id747ef484dfdcb2d346f817976f52073912468d0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/glados/variants/lars/variant.c')
| -rw-r--r-- | src/mainboard/google/glados/variants/lars/variant.c | 24 |
1 files changed, 10 insertions, 14 deletions
diff --git a/src/mainboard/google/glados/variants/lars/variant.c b/src/mainboard/google/glados/variants/lars/variant.c index 37860c3738..c24950d814 100644 --- a/src/mainboard/google/glados/variants/lars/variant.c +++ b/src/mainboard/google/glados/variants/lars/variant.c @@ -28,9 +28,11 @@ #define MEM_SINGLE_CHANB 0xb #define MEM_SINGLE_CHANC 0xc -void variant_memory_init_params( - MEMORY_INIT_UPD *const params, const int spd_index) +void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index) { + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + /* DQ byte map */ const u8 dq_map[2][12] = { { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, @@ -58,18 +60,12 @@ void variant_memory_init_params( if (spd_index == K4E6E304EB_MEM_ID) targeted_rcomp = StrengthendRcompTarget; - memcpy(params->DqByteMapCh0, dq_map[0], - sizeof(params->DqByteMapCh0)); - memcpy(params->DqByteMapCh1, dq_map[1], - sizeof(params->DqByteMapCh1)); - memcpy(params->DqsMapCpu2DramCh0, dqs_map[0], - sizeof(params->DqsMapCpu2DramCh0)); - memcpy(params->DqsMapCpu2DramCh1, dqs_map[1], - sizeof(params->DqsMapCpu2DramCh1)); - memcpy(params->RcompResistor, RcompResistor, - sizeof(params->RcompResistor)); - memcpy(params->RcompTarget, targeted_rcomp, - sizeof(params->RcompTarget)); + memcpy(mem_cfg->DqByteMapCh0, dq_map[0], sizeof(mem_cfg->DqByteMapCh0)); + memcpy(mem_cfg->DqByteMapCh1, dq_map[1], sizeof(mem_cfg->DqByteMapCh1)); + memcpy(mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(mem_cfg->DqsMapCpu2DramCh0)); + memcpy(mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(mem_cfg->DqsMapCpu2DramCh1)); + memcpy(mem_cfg->RcompResistor, RcompResistor, sizeof(mem_cfg->RcompResistor)); + memcpy(mem_cfg->RcompTarget, RcompTarget, sizeof(mem_cfg->RcompTarget)); } int is_dual_channel(const int spd_index) |