google/chell: Convert to a variant of glados

Convert chell to a variant of glados Skylake reference board:
- add chell-specific DPTF, EC config, USB port defs, GPIO config,
    NHLT config, PEI data, VBT, SPD data, and devicetree
- add romstage handler to turn on keyboard backlight for boards
    so equipped
- remove existing chell board/directory

Test: build/boot google/chell, verify functionality unchanged
from pre-variant configuration

Change-Id: I7dfbafe3afcab7cee7bcb2bf91c6733c07b409c4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

2 files changed, 250 insertions, 0 deletions

diff --git a/src/mainboard/google/glados/variants/chell/include/variant/acpi/dptf.asl b/src/mainboard/google/glados/variants/chell/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000000..ad370982ab
--- /dev/null
+++ b/src/mainboard/google/glados/variants/chell/include/variant/acpi/dptf.asl
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE        80
+#define DPTF_CPU_CRITICAL       99
+
+#define DPTF_TSR0_SENSOR_ID	1
+#define DPTF_TSR0_SENSOR_NAME	"Ambient"
+#define DPTF_TSR0_PASSIVE	55
+#define DPTF_TSR0_CRITICAL	70
+
+#define DPTF_TSR1_SENSOR_ID	2
+#define DPTF_TSR1_SENSOR_NAME	"Charger"
+#define DPTF_TSR1_PASSIVE	55
+#define DPTF_TSR1_CRITICAL	75
+
+#define DPTF_TSR2_SENSOR_ID	3
+#define DPTF_TSR2_SENSOR_NAME	"DRAM"
+#define DPTF_TSR2_PASSIVE	52
+#define DPTF_TSR2_CRITICAL	75
+
+#define DPTF_TSR3_SENSOR_ID	4
+#define DPTF_TSR3_SENSOR_NAME	"WiFi"
+#define DPTF_TSR3_PASSIVE	55
+#define DPTF_TSR3_CRITICAL	70
+
+/* SKL-Y is Fanless design. */
+#undef DPTF_ENABLE_FAN_CONTROL
+
+/* Enable DPTF charger control */
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+	Package () { 0, 0, 0, 0, 255, 0x7b7, "mA", 0 },	/* 1975mA (MAX) */
+	Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },	/* 1500mA */
+	Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },	/* 1000mA */
+	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 500mA */
+	Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 },	/* 0mA */
+})
+
+Name (DTRT, Package () {
+	/* CPU Throttle Effect on CPU */
+	Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 0 */
+	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 1 */
+	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 2 */
+	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 90, 0, 0, 0, 0 },
+
+	/* CPU Effect on Temp Sensor 3 */
+	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+	0x2,		/* Revision */
+	Package () {	/* Power Limit 1 */
+		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
+		3000,	/* PowerLimitMinimum */
+		6000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		250	/* StepSize */
+	},
+	Package () {	/* Power Limit 2 */
+		1,	/* PowerLimitIndex, 1 for Power Limit 2 */
+		15000,	/* PowerLimitMinimum */
+		15000,	/* PowerLimitMaximum */
+		1000,	/* TimeWindowMinimum */
+		1000,	/* TimeWindowMaximum */
+		1000	/* StepSize */
+	}
+})
diff --git a/src/mainboard/google/glados/variants/chell/include/variant/acpi/mainboard.asl b/src/mainboard/google/glados/variants/chell/include/variant/acpi/mainboard.asl
new file mode 100644
index 0000000000..aa465fae4f
--- /dev/null
+++ b/src/mainboard/google/glados/variants/chell/include/variant/acpi/mainboard.asl
@@ -0,0 +1,159 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB.PCI0.XHCI.RHUB.HS01)
+{
+	// Left Rear USB 2.0 Type-C
+	Name (_UPC, Package (0x04)
+	{
+		0xFF,	// Connectable
+		Zero,	// USB Port
+		Zero,	// Reserved
+		Zero	// Reserved
+	})
+
+	// Visible
+	Method (_PLD, 0, NotSerialized)
+	{
+		Return (GPLD (One))
+	}
+}
+Scope (\_SB.PCI0.XHCI.RHUB.HS02)
+{
+	// Left Rear USB 2.0 Type-C
+	Name (_UPC, Package (0x04)
+	{
+		0xFF,	// Connectable
+		Zero,	// USB Port
+		Zero,	// Reserved
+		Zero	// Reserved
+	})
+
+	// Visible
+	Method (_PLD, 0, NotSerialized)
+	{
+		Return (GPLD (One))
+	}
+}
+Scope (\_SB.PCI0.XHCI.RHUB.HS03)
+{
+	// Bluetooth
+	Name (_UPC, Package (0x04)
+	{
+		0xFF,	// Connectable
+		0xFF,	// OEM Connector
+		Zero,	// Reserved
+		Zero	// Reserved
+	})
+
+	// Not Visible
+	Method (_PLD, 0, NotSerialized)
+	{
+		Return (GPLD (Zero))
+	}
+}
+Scope (\_SB.PCI0.XHCI.RHUB.HS04)
+{
+	// SD Card
+	Name (_UPC, Package (0x04)
+	{
+		0xFF,	// Connectable
+		0xFF,	// OEM Connector
+		Zero,	// Reserved
+		Zero	// Reserved
+	})
+
+	// Not Visible
+	Method (_PLD, 0, NotSerialized)
+	{
+		Return (GPLD (Zero))
+	}
+}
+Scope (\_SB.PCI0.XHCI.RHUB.HS05)
+{
+	// Left USB 2.0 Type-A
+	Name (_UPC, Package (0x04)
+	{
+		0xFF,	// Connectable
+		Zero,	// USB Port
+		Zero,	// Reserved
+		Zero	// Reserved
+	})
+
+	// Visible
+	Method (_PLD, 0, NotSerialized)
+	{
+		Return (GPLD (One))
+	}
+}
+Scope (\_SB.PCI0.XHCI.RHUB.HS07)
+{
+	// Webcam
+	Name (_UPC, Package (0x04)
+	{
+		0xFF,	// Connectable
+		0xFF,	// OEM Connector
+		Zero,	// Reserved
+		Zero	// Reserved
+	})
+
+	// Not Visible
+	Method (_PLD, 0, NotSerialized)
+	{
+		Return (GPLD (Zero))
+	}
+}
+Scope (\_SB.PCI0.XHCI.RHUB.SS01)
+{
+	// Left Rear USB 3.0 Type-C
+	Name (_UPC, Package (0x04)
+	{
+		0xFF,	// Connectable
+		0x03,	// USB 3.0 Port
+		Zero,	// Reserved
+		Zero	// Reserved
+	})
+}
+Scope (\_SB.PCI0.XHCI.RHUB.SS02)
+{
+	// Left Front USB 3.0 Type-C
+	Name (_UPC, Package (0x04)
+	{
+		0xFF,	// Connectable
+		0x03,	// USB 3.0 Port
+		Zero,	// Reserved
+		Zero	// Reserved
+	})
+}
+Scope (\_SB.PCI0.XHCI.RHUB.SS03)
+{
+	// Left USB 3.0 Type-A
+	Name (_UPC, Package (0x04)
+	{
+		0xFF,	// Connectable
+		0x03,	// USB 3.0 Port
+		Zero,	// Reserved
+		Zero	// Reserved
+	})
+}
+Scope (\_SB.PCI0.XHCI.RHUB.SS04)
+{
+	// SD Card
+	Name (_UPC, Package (0x04)
+	{
+		0xFF,	// Connectable
+		0x03,	// USB 3.0
+		Zero,	// Reserved
+		Zero	// Reserved
+	})
+}