mb/google/glados: port to FSP 2.0

This patch is part of the patch series to drop support for FSP 1.1 in
soc/intel/skylake.

The following modifications have been done to migrate the board(s) from
FSP 1.1 to FSP 2.0:

- remove deprecated devicetree VR_RING domain (only 4 domains in FSP 2.0)
- switch to using the FSP default VBT

TODO:
- testing

Change-Id: Id747ef484dfdcb2d346f817976f52073912468d0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 10 insertions, 14 deletions

diff --git a/src/mainboard/google/glados/variants/cave/variant.c b/src/mainboard/google/glados/variants/cave/variant.c
index d63a298df7..d625f1700a 100644
--- a/src/mainboard/google/glados/variants/cave/variant.c
+++ b/src/mainboard/google/glados/variants/cave/variant.c
@@ -21,9 +21,11 @@
 #include <string.h>
 #include <variant/gpio.h>
 
-void variant_memory_init_params(
-		MEMORY_INIT_UPD *const memory_params, const int spd_index)
+void variant_memory_init_params(FSPM_UPD *mupd, const int spd_index)
 {
+	FSP_M_CONFIG *mem_cfg;
+	mem_cfg = &mupd->FspmConfig;
+
 	/* DQ byte map */
 	const u8 dq_map[2][12] = {
 		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
@@ -41,18 +43,12 @@ void variant_memory_init_params(
 	/* Rcomp target */
 	const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };
 
-	memcpy(memory_params->DqByteMapCh0, dq_map[0],
-			sizeof(memory_params->DqByteMapCh0));
-	memcpy(memory_params->DqByteMapCh1, dq_map[1],
-			sizeof(memory_params->DqByteMapCh1));
-	memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0],
-			sizeof(memory_params->DqsMapCpu2DramCh0));
-	memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1],
-			sizeof(memory_params->DqsMapCpu2DramCh1));
-	memcpy(memory_params->RcompResistor, RcompResistor,
-			sizeof(memory_params->RcompResistor));
-	memcpy(memory_params->RcompTarget, RcompTarget,
-			sizeof(memory_params->RcompTarget));
+	memcpy(mem_cfg->DqByteMapCh0, dq_map[0], sizeof(mem_cfg->DqByteMapCh0));
+	memcpy(mem_cfg->DqByteMapCh1, dq_map[1], sizeof(mem_cfg->DqByteMapCh1));
+	memcpy(mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(mem_cfg->DqsMapCpu2DramCh0));
+	memcpy(mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(mem_cfg->DqsMapCpu2DramCh1));
+	memcpy(mem_cfg->RcompResistor, RcompResistor, sizeof(mem_cfg->RcompResistor));
+	memcpy(mem_cfg->RcompTarget, RcompTarget, sizeof(mem_cfg->RcompTarget));
 }
 
 void mainboard_gpio_smi_sleep(void)