soc/intel,mb/*: get rid of legacy pad macros

Get rid of legacy pad macros by replacing them with their newer
equivalents.

TEST: TIMELESS-built board images match

Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

1 files changed, 91 insertions, 91 deletions

diff --git a/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h b/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h
index 1f4bd6565a..24e7b33cc2 100644
--- a/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h
+++ b/src/mainboard/google/glados/variants/caroline/include/variant/gpio.h
@@ -57,64 +57,64 @@
 /* Pad configuration in ramstage. */
 static const struct pad_config gpio_table[] = {
 /* RCIN# */		PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
-/* LAD0 */		PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1),
-/* LAD1 */		PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1),
-/* LAD2 */		PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1),
-/* LAD3 */		PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1),
+/* LAD0 */		PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
+/* LAD1 */		PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
+/* LAD2 */		PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
+/* LAD3 */		PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
 /* LFRAME# */		PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
 /* SERIRQ */		PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
-/* PIRQA# */		PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, 20K_PU, DEEP), /* SD_CD_INT_L */
+/* PIRQA# */		PAD_CFG_GPI_GPIO_DRIVER(GPP_A7, UP_20K, DEEP), /* SD_CD_INT_L */
 /* CLKRUN# */		PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
 /* CLKOUT_LPC0 */	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
-/* CLKOUT_LPC1 */	PAD_CFG_NC(GPP_A10),
-/* PME# */		PAD_CFG_NC(GPP_A11),
-/* BM_BUSY# */		PAD_CFG_NC(GPP_A12),
+/* CLKOUT_LPC1 */	PAD_NC(GPP_A10, NONE),
+/* PME# */		PAD_NC(GPP_A11, NONE),
+/* BM_BUSY# */		PAD_NC(GPP_A12, NONE),
 /* SUSWARN# */		PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
 /* SUS_STAT# */		PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
 /* SUSACK# */		PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
 /* SD_1P8_SEL */	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
 /* SD_PWR_EN# */	PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
-/* ISH_GP0 */		PAD_CFG_NC(GPP_A18),
-/* ISH_GP1 */		PAD_CFG_NC(GPP_A19),
-/* ISH_GP2 */		PAD_CFG_NC(GPP_A20),
-/* ISH_GP3 */		PAD_CFG_NC(GPP_A21),
-/* ISH_GP4 */		PAD_CFG_NC(GPP_A22),
-/* ISH_GP5 */		PAD_CFG_NC(GPP_A23),
-/* CORE_VID0 */		PAD_CFG_NC(GPP_B0),
-/* CORE_VID1 */		PAD_CFG_NC(GPP_B1),
-/* VRALERT# */		PAD_CFG_NC(GPP_B2),
-/* CPU_GP2 */		PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), /* TOUCHPAD */
-/* CPU_GP3 */		PAD_CFG_NC(GPP_B4),
-/* SRCCLKREQ0# */	PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */
+/* ISH_GP0 */		PAD_NC(GPP_A18, NONE),
+/* ISH_GP1 */		PAD_NC(GPP_A19, NONE),
+/* ISH_GP2 */		PAD_NC(GPP_A20, NONE),
+/* ISH_GP3 */		PAD_NC(GPP_A21, NONE),
+/* ISH_GP4 */		PAD_NC(GPP_A22, NONE),
+/* ISH_GP5 */		PAD_NC(GPP_A23, NONE),
+/* CORE_VID0 */		PAD_NC(GPP_B0, NONE),
+/* CORE_VID1 */		PAD_NC(GPP_B1, NONE),
+/* VRALERT# */		PAD_NC(GPP_B2, NONE),
+/* CPU_GP2 */		PAD_CFG_GPI_APIC_HIGH(GPP_B3, NONE, PLTRST), /* TOUCHPAD */
+/* CPU_GP3 */		PAD_NC(GPP_B4, NONE),
+/* SRCCLKREQ0# */	PAD_CFG_GPI_SCI(GPP_B5, NONE, DEEP, EDGE_SINGLE, INVERT), /* TOUCHPAD WAKE */
 /* SRCCLKREQ1# */	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN */
-/* SRCCLKREQ2# */	PAD_CFG_NC(GPP_B7),
-/* SRCCLKREQ3# */	PAD_CFG_NC(GPP_B8),
-/* SRCCLKREQ4# */	PAD_CFG_NC(GPP_B9),
-/* SRCCLKREQ5# */	PAD_CFG_NC(GPP_B10),
-/* EXT_PWR_GATE# */	PAD_CFG_NC(GPP_B11),
+/* SRCCLKREQ2# */	PAD_NC(GPP_B7, NONE),
+/* SRCCLKREQ3# */	PAD_NC(GPP_B8, NONE),
+/* SRCCLKREQ4# */	PAD_NC(GPP_B9, NONE),
+/* SRCCLKREQ5# */	PAD_NC(GPP_B10, NONE),
+/* EXT_PWR_GATE# */	PAD_NC(GPP_B11, NONE),
 /* SLP_S0# */		PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
 /* PLTRST# */		PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
-/* SPKR */		PAD_CFG_NC(GPP_B14),
-/* GSPI0_CS# */		PAD_CFG_GPI_ACPI_SCI(GPP_B15, NONE, DEEP, NONE), /* DIG EJECT */
-/* GSPI0_CLK */		PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */
-/* GSPI0_MISO */	PAD_CFG_NC(GPP_B17),
-/* GSPI0_MOSI */	PAD_CFG_NC(GPP_B18),
+/* SPKR */		PAD_NC(GPP_B14, NONE),
+/* GSPI0_CS# */		PAD_CFG_GPI_SCI(GPP_B15, NONE, DEEP, EDGE_SINGLE, NONE), /* DIG EJECT */
+/* GSPI0_CLK */		PAD_CFG_GPI_SCI(GPP_B16, NONE, DEEP, EDGE_SINGLE, INVERT), /* WLAN WAKE */
+/* GSPI0_MISO */	PAD_NC(GPP_B17, NONE),
+/* GSPI0_MOSI */	PAD_NC(GPP_B18, NONE),
 /* GSPI1_CS# */		PAD_CFG_GPI_GPIO_DRIVER(GPP_B19, NONE, DEEP), /* non-wake DIG EJECT */
-/* GSPI1_CLK */		PAD_CFG_NC(GPP_B20),
-/* GSPI1_MISO */	PAD_CFG_NC(GPP_B21),
-/* GSPI1_MOSI */	PAD_CFG_NC(GPP_B22),
-/* SM1ALERT# */		PAD_CFG_NC(GPP_B23),
+/* GSPI1_CLK */		PAD_NC(GPP_B20, NONE),
+/* GSPI1_MISO */	PAD_NC(GPP_B21, NONE),
+/* GSPI1_MOSI */	PAD_NC(GPP_B22, NONE),
+/* SM1ALERT# */		PAD_NC(GPP_B23, NONE),
 /* SMBCLK */		PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */
 /* SMBDATA */		PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */
-/* SMBALERT# */		PAD_CFG_NC(GPP_C2),
-/* SML0CLK */		PAD_CFG_NC(GPP_C3),
-/* SML0DATA */		PAD_CFG_NC(GPP_C4),
-/* SML0ALERT# */	PAD_CFG_NC(GPP_C5),
-/* SM1CLK */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
-/* SM1DATA */		PAD_CFG_NC(GPP_C7),
-/* UART0_RXD */		PAD_CFG_NC(GPP_C8),
-/* UART0_TXD */		PAD_CFG_NC(GPP_C9),
-/* UART0_RTS# */	PAD_CFG_NC(GPP_C10),
+/* SMBALERT# */		PAD_NC(GPP_C2, NONE),
+/* SML0CLK */		PAD_NC(GPP_C3, NONE),
+/* SML0DATA */		PAD_NC(GPP_C4, NONE),
+/* SML0ALERT# */	PAD_NC(GPP_C5, NONE),
+/* SM1CLK */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), /* EC_IN_RW */
+/* SM1DATA */		PAD_NC(GPP_C7, NONE),
+/* UART0_RXD */		PAD_NC(GPP_C8, NONE),
+/* UART0_TXD */		PAD_NC(GPP_C9, NONE),
+/* UART0_RTS# */	PAD_NC(GPP_C10, NONE),
 /* UART0_CTS# */	PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_DX_DIG */
 /* UART1_RXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
 /* UART1_TXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */
@@ -127,55 +127,55 @@ static const struct pad_config gpio_table[] = {
 /* UART2_RXD */		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
 /* UART2_TXD */		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
 /* UART2_RTS# */	PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */
-/* UART2_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
-/* SPI1_CS# */		PAD_CFG_NC(GPP_D0),
-/* SPI1_CLK */		PAD_CFG_NC(GPP_D1),
-/* SPI1_MISO */		PAD_CFG_NC(GPP_D2),
-/* SPI1_MOSI */		PAD_CFG_NC(GPP_D3),
-/* FASHTRIG */		PAD_CFG_NC(GPP_D4),
+/* UART2_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */
+/* SPI1_CS# */		PAD_NC(GPP_D0, NONE),
+/* SPI1_CLK */		PAD_NC(GPP_D1, NONE),
+/* SPI1_MISO */		PAD_NC(GPP_D2, NONE),
+/* SPI1_MOSI */		PAD_NC(GPP_D3, NONE),
+/* FASHTRIG */		PAD_NC(GPP_D4, NONE),
 /* ISH_I2C0_SDA */	PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */
 /* ISH_I2C0_SCL */	PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */
-/* ISH_I2C1_SDA */	PAD_CFG_NC(GPP_D7),
-/* ISH_I2C1_SCL */	PAD_CFG_NC(GPP_D8),
-/* ISH_SPI_CS# */	PAD_CFG_NC(GPP_D9),
-/* ISH_SPI_CLK */	PAD_CFG_NC(GPP_D10),
-/* ISH_SPI_MISO */	PAD_CFG_NC(GPP_D11),
+/* ISH_I2C1_SDA */	PAD_NC(GPP_D7, NONE),
+/* ISH_I2C1_SCL */	PAD_NC(GPP_D8, NONE),
+/* ISH_SPI_CS# */	PAD_NC(GPP_D9, NONE),
+/* ISH_SPI_CLK */	PAD_NC(GPP_D10, NONE),
+/* ISH_SPI_MISO */	PAD_NC(GPP_D11, NONE),
 /* ISH_SPI_MOSI */	PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */
-/* ISH_UART0_RXD */	PAD_CFG_NC(GPP_D13),
-/* ISH_UART0_TXD */	PAD_CFG_NC(GPP_D14),
-/* ISH_UART0_RTS# */	PAD_CFG_NC(GPP_D15),
-/* ISH_UART0_CTS# */	PAD_CFG_NC(GPP_D16),
-/* DMIC_CLK1 */		PAD_CFG_NC(GPP_D17),
-/* DMIC_DATA1 */	PAD_CFG_NC(GPP_D18),
+/* ISH_UART0_RXD */	PAD_NC(GPP_D13, NONE),
+/* ISH_UART0_TXD */	PAD_NC(GPP_D14, NONE),
+/* ISH_UART0_RTS# */	PAD_NC(GPP_D15, NONE),
+/* ISH_UART0_CTS# */	PAD_NC(GPP_D16, NONE),
+/* DMIC_CLK1 */		PAD_NC(GPP_D17, NONE),
+/* DMIC_DATA1 */	PAD_NC(GPP_D18, NONE),
 /* DMIC_CLK0 */		PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
 /* DMIC_DATA0 */	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
-/* TS_SPI1_IO2 */	PAD_CFG_NC(GPP_D21),
+/* TS_SPI1_IO2 */	PAD_NC(GPP_D21, NONE),
 /* TS_SPI1_IO3 */	PAD_CFG_GPO(GPP_D22, 1, DEEP), /* I2S2 BUFFER */
 /* I2S_MCLK */		PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
-/* SATAXPCI0 */		PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */
-/* SATAXPCIE1 */	PAD_CFG_NC(GPP_E1),
-/* SATAXPCIE2 */	PAD_CFG_NC(GPP_E2),
-/* CPU_GP0 */		PAD_CFG_NC(GPP_E3),
-/* SATA_DEVSLP0 */	PAD_CFG_NC(GPP_E4),
-/* SATA_DEVSLP1 */	PAD_CFG_NC(GPP_E5),
-/* SATA_DEVSLP2 */	PAD_CFG_NC(GPP_E6),
-/* CPU_GP1 */		PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN */
-/* SATALED# */		PAD_CFG_NC(GPP_E8),
-/* USB2_OCO# */		PAD_CFG_NC(GPP_E9),
-/* USB2_OC1# */		PAD_CFG_NC(GPP_E10),
+/* SATAXPCI0 */		PAD_CFG_GPI_APIC_HIGH(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */
+/* SATAXPCIE1 */	PAD_NC(GPP_E1, NONE),
+/* SATAXPCIE2 */	PAD_NC(GPP_E2, NONE),
+/* CPU_GP0 */		PAD_NC(GPP_E3, NONE),
+/* SATA_DEVSLP0 */	PAD_NC(GPP_E4, NONE),
+/* SATA_DEVSLP1 */	PAD_NC(GPP_E5, NONE),
+/* SATA_DEVSLP2 */	PAD_NC(GPP_E6, NONE),
+/* CPU_GP1 */		PAD_CFG_GPI_APIC_HIGH(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN */
+/* SATALED# */		PAD_NC(GPP_E8, NONE),
+/* USB2_OCO# */		PAD_NC(GPP_E9, NONE),
+/* USB2_OC1# */		PAD_NC(GPP_E10, NONE),
 /* USB2_OC2# */		PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
 /* USB2_OC3# */		PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
 /* DDPB_HPD0 */		PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
 /* DDPC_HPD1 */		PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
-/* DDPD_HPD2 */		PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */
-/* DDPE_HPD3 */		PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */
+/* DDPD_HPD2 */		PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SMI_L */
+/* DDPE_HPD3 */		PAD_CFG_GPI_SCI(GPP_E16, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC_SCI_L */
 /* EDP_HPD */		PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
-/* DDPB_CTRLCLK */	PAD_CFG_NC(GPP_E18),
-/* DDPB_CTRLDATA */	PAD_CFG_NC(GPP_E19),
-/* DDPC_CTRLCLK */	PAD_CFG_NC(GPP_E20),
-/* DDPC_CTRLDATA */	PAD_CFG_NC(GPP_E21),
-/* DDPD_CTRLCLK */	PAD_CFG_NC(GPP_E22),
-/* DDPD_CTRLDATA */	PAD_CFG_NC(GPP_E23),
+/* DDPB_CTRLCLK */	PAD_NC(GPP_E18, NONE),
+/* DDPB_CTRLDATA */	PAD_NC(GPP_E19, NONE),
+/* DDPC_CTRLCLK */	PAD_NC(GPP_E20, NONE),
+/* DDPC_CTRLDATA */	PAD_NC(GPP_E21, NONE),
+/* DDPD_CTRLCLK */	PAD_NC(GPP_E22, NONE),
+/* DDPD_CTRLDATA */	PAD_NC(GPP_E23, NONE),
 /*
  * The next 4 pads are for bit banging the amplifiers. They are connected
  * together with i2s0 signals. For default behavior of i2s make these
@@ -187,12 +187,12 @@ static const struct pad_config gpio_table[] = {
 /* I2S2_RXD */		PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP),
 /* I2C2_SDA */		PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* DIG */
 /* I2C2_SCL */		PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* DIG */
-/* I2C3_SDA */		PAD_CFG_NC(GPP_F6),
-/* I2C3_SCL */		PAD_CFG_GPI_APIC(GPP_F7, NONE, PLTRST), /* DIG_PDCT_L */
+/* I2C3_SDA */		PAD_NC(GPP_F6, NONE),
+/* I2C3_SCL */		PAD_CFG_GPI_APIC_HIGH(GPP_F7, NONE, PLTRST), /* DIG_PDCT_L */
 /* I2C4_SDA */		PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* Amplifiers */
 /* I2C4_SCL */		PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* Amplifiers */
-/* I2C5_SDA */		PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */
-/* I2C5_SCL */		PAD_CFG_GPI_APIC(GPP_F11, NONE, PLTRST), /* DIG_IRQ_L */
+/* I2C5_SDA */		PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), /* MIC_INT_L */
+/* I2C5_SCL */		PAD_CFG_GPI_APIC_HIGH(GPP_F11, NONE, PLTRST), /* DIG_IRQ_L */
 /* EMMC_CMD */		PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
 /* EMMC_DATA0 */	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
 /* EMMC_DATA1 */	PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
@@ -204,7 +204,7 @@ static const struct pad_config gpio_table[] = {
 /* EMMC_DATA7 */	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
 /* EMMC_RCLK */		PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
 /* EMMC_CLK */		PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
-/* RSVD */		PAD_CFG_NC(GPP_F23),
+/* RSVD */		PAD_NC(GPP_F23, NONE),
 /* SD_CMD */		PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
 /* SD_DATA0 */		PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
 /* SD_DATA1 */		PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
@@ -216,7 +216,7 @@ static const struct pad_config gpio_table[] = {
  * SD write protect is not connected but is still sampled, so enable
  * native function and enable internal pull-down to disable.
  */
-/* SD_WP */		PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1),
+/* SD_WP */		PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1),
 /* BATLOW# */		PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
 /* ACPRESENT */		PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
 /* LAN_WAKE# */		PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */
@@ -224,16 +224,16 @@ static const struct pad_config gpio_table[] = {
 /* SLP_S3# */		PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
 /* SLP_S4# */		PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
 /* SLP_A# */		PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
-/* RSVD */		PAD_CFG_NC(GPD7),
+/* RSVD */		PAD_NC(GPD7, NONE),
 /* SUSCLK */		PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
-/* SLP_WLAN# */		PAD_CFG_NC(GPD9),
-/* SLP_S5# */		PAD_CFG_NC(GPD10),
-/* LANPHYC */		PAD_CFG_NC(GPD11),
+/* SLP_WLAN# */		PAD_NC(GPD9, NONE),
+/* SLP_S5# */		PAD_NC(GPD10, NONE),
+/* LANPHYC */		PAD_NC(GPD11, NONE),
 };
 
 /* Early pad configuration in romstage. */
 static const struct pad_config early_gpio_table[] = {
-/* UART2_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
+/* UART2_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), /* PCH_WP */
 };
 
 #endif